JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide

Download PDF
ID 683113
Date 10/14/2022
Public
Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide
1. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide x
1.1. JESD204B Intel® Arria® 10 FPGA IP Design Example Quick Start Guide 1.2. Design Example Detailed Description 1.3. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide Document Archives 1.4. Document Revision History for the JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide
1.1. JESD204B Intel® Arria® 10 FPGA IP Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Design Example Parameters
1.1.4. Compiling and Testing the Design x
1.1.4.1. Hardware Test for System Console Control Design Example 1.1.4.2. Hardware Test for Nios Control Design Example
1.2. Design Example Detailed Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Supported Configurations 1.2.4. Presets 1.2.5. Functional Description 1.2.6. Simulation 1.2.7. Design Example Files 1.2.8. Registers 1.2.9. Signals 1.2.10. Software Control Flow 1.2.11. Customizing the Design Example
1.2.5. Functional Description x
1.2.5.1. Design Components 1.2.5.2. Clocking Scheme
1.2.5.1. Design Components x
1.2.5.1.1. Platform Designer System Component 1.2.5.1.2. Transport Layer 1.2.5.1.3. Test Pattern Generator 1.2.5.1.4. Test Pattern Checker
1.2.5.1.1. Platform Designer System Component x
1.2.5.1.1.1. JESD204B Subsystem in Platform Designer 1.2.5.1.1.2. Parallel I/O 1.2.5.1.1.3. ATX PLL 1.2.5.1.1.4. Core PLL 1.2.5.1.1.5. SPI Master 1.2.5.1.1.6. Nios Subsystem
1.2.6. Simulation x
1.2.6.1. Testbench
1.2.10. Software Control Flow x
1.2.10.1. Software Parameters 1.2.10.2. Interrupt Service Routines (ISR) 1.2.10.3. Software Functions Description
1.2.10.3. Software Functions Description x
1.2.10.3.1. Functions in main.c Source File 1.2.10.3.2. Custom Peripheral Access Macros in macros.c Source File
1.2.11. Customizing the Design Example x
1.2.11.1. Modifying the JESD204B IP Core Parameters 1.2.11.2. Changing the Data Rate or Reference Clock Frequency
1. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide

1.1.4.1. Hardware Test for System Console Control Design Example

Perform the following instructions to run the hardware test for the design example using the System Control tool.
Note: This hardware test assumes that the System Console Control design is configured in duplex mode. Make your own modifications if using simplex mode design.
  1. Launch the System Console tool from Intel® Quartus® Prime (Tools > System Debugging Tools > System Console).
  2. In the TCL Console command prompt, type get_service_paths master to print a list of devices connected to your JTAG chain.
  3. Open the main.tcl Tcl script located in the System Console directory in any text editor of your choice and locate the following line. 
    set master_index [expr {$master_list_length - <your offset>}]
  4. Adjust the master_index offset as necessary to reflect your JTAG chain configuration such that the master_index always points to the Intel® Arria® 10 device and save the file.
  5. In the TCL Console command prompt, navigate to the system_console directory (cd system_console) and execute the main.tcl script (source main.tcl). Your TCL Console window should resemble the following figure.
    Figure 5. Source main.tcl
  6. Type start_basic_test at the command prompt to execute the link setup and test procedure.
    This procedure executes a set of instructions to set up the pattern generator and checker to transmit and check PRBS pattern, configure the JESD204B IP PHY internal serial loopback mode and report link status.
    The following figure illustrates the expected result from a successful link setup and test.
    Figure 6. Successful Test in the System Console
  7. In the event that the test fails due to a lane deskew error, use the rbd_offset procedure (described in the following table) to offset the default RBD setting. Refer to the JESD204B Intel® FPGA IP User Guide for more details on using the RBD offset.
    Table 4.  Procedures in the main.tcl System Console Script The table describes useful procedures in the main.tcl that may be helpful in debugging.
    Procedure Values Description
    get_service_paths {master} Reports all devices that are connected to the JTAG chain. Use this information to set the master index to point to the Intel® Arria® 10 device
    get_master_index N/A Set the targeted device master index. Use get_service_paths master to determine the offset of the Intel® Arria® 10 device in the JTAG chain, and edit the offset in this procedure accordingly.
    start_basic_test N/A Main procedure that sets up link serial loopback mode, pattern generator and checker test mode, pulses sysref and reports link status
    reset N/A Global reset
    force_link_frame_reset {0,1}

    0: Deassert link and frame resets

    1: Assert and hold link and frame resets

    Note: Link and frame clock domains should be held in reset while writing to JESD204B IP CSR
    sloopback {0,1}

    0: Disable internal serial loopback

    1: Enable internal serial loopback
    set_testmode {alt, ramp, prbs}

    alt: Set pattern generator and checker to alternate pattern

    ramp: Set pattern generator and checker to ramp pattern

    prbs: Set pattern generator and checker to PRBS pattern

    rbd_offset {integer} Adjust RBD offset value to eliminate RX lane deskew error.
    sysref N/A Single pulse sysref
    read_status_pio N/A

    Read status PIO registers. PIO status configuration:

    Bit 0 — Core PLL locked

    Bit 1 — TX transceiver ready

    Bit 2 — RX transceiver ready

    Bit 3 — Pattern checker mismatch error

    Bit 4 — TX link error (use read_err_status procedure to report error description)

    Bit 5 — RX link error (use read_err_status procedure to report error description)

    read_err_status N/A Read JESD204B IP error status registers. Refer to the JESD204B IP register maps for detailed description of status registers.
    clear_err_status N/A Clear JESD204B IP error status registers
    read_rx_status0 N/A Read JESD204B IP rx_status0 register. Refer to the JESD204B IP register maps for detailed description of status registers
    read_tx_status0 N/A Read JESD204B IP tx_status0 register. Refer to the JESD204B IP register maps for detailed description of status registers.
    read_rx_syncn_sysref_ctrl N/A Read JESD204B IP syncn_sysref_ctrl register. Refer to the JESD204B IP register maps for detailed description of status registers
    wait_seconds {integer} Wait for {integer} seconds
    wait_minutes {integer} Wait for {integer} minutes
Related Information
Level Two Title