JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide

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ID 683113
Date 10/14/2022
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide
1. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide x
1.1. JESD204B Intel® Arria® 10 FPGA IP Design Example Quick Start Guide 1.2. Design Example Detailed Description 1.3. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide Document Archives 1.4. Document Revision History for the JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide
1.1. JESD204B Intel® Arria® 10 FPGA IP Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Design Example Parameters
1.1.4. Compiling and Testing the Design x
1.1.4.1. Hardware Test for System Console Control Design Example 1.1.4.2. Hardware Test for Nios Control Design Example
1.2. Design Example Detailed Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Supported Configurations 1.2.4. Presets 1.2.5. Functional Description 1.2.6. Simulation 1.2.7. Design Example Files 1.2.8. Registers 1.2.9. Signals 1.2.10. Software Control Flow 1.2.11. Customizing the Design Example
1.2.5. Functional Description x
1.2.5.1. Design Components 1.2.5.2. Clocking Scheme
1.2.5.1. Design Components x
1.2.5.1.1. Platform Designer System Component 1.2.5.1.2. Transport Layer 1.2.5.1.3. Test Pattern Generator 1.2.5.1.4. Test Pattern Checker
1.2.5.1.1. Platform Designer System Component x
1.2.5.1.1.1. JESD204B Subsystem in Platform Designer 1.2.5.1.1.2. Parallel I/O 1.2.5.1.1.3. ATX PLL 1.2.5.1.1.4. Core PLL 1.2.5.1.1.5. SPI Master 1.2.5.1.1.6. Nios Subsystem
1.2.6. Simulation x
1.2.6.1. Testbench
1.2.10. Software Control Flow x
1.2.10.1. Software Parameters 1.2.10.2. Interrupt Service Routines (ISR) 1.2.10.3. Software Functions Description
1.2.10.3. Software Functions Description x
1.2.10.3.1. Functions in main.c Source File 1.2.10.3.2. Custom Peripheral Access Macros in macros.c Source File
1.2.11. Customizing the Design Example x
1.2.11.1. Modifying the JESD204B IP Core Parameters 1.2.11.2. Changing the Data Rate or Reference Clock Frequency
1. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide

1.1.4.2. Hardware Test for Nios Control Design Example

Follow the instructions below to run the hardware test for the Nios Control design example.

Note: This hardware test assumes that the Nios Control design is configured in duplex mode. Make your own modifications if using simplex mode design.
  1. 1. Launch the Nios II Software Build Tools for Eclipse tool from Intel® Quartus® Prime (Tools > Nios II Software Build Tools for Eclipse).
  2. In the Select a workspace dialog box, navigate to the software workspace <design example>/software.
  3. Create a new Nios II application and board support package (BSP) from the template (File > New > Nios II Application and BSP From Template ).
  4. In the Nios II Application and BSP From Template window, enter the following information:
    1. SOPC Information File Name: <design example>/altera_jesd204_ed_qsys_RX_TX/altera_jesd204_ed_qsys_RX_TX.sopcinfo
    2. Project name: <software project>
    3. User default location: Checked
    4. Templates: Blank Project
  5. Click Next. Verify that the default BSP name is <software project>_bsp, then click Finish. The Nios II application project and BSP appears in the Project Explorer window.
  6. In the Project Explorer window, right-click the <software project>_bsp project, navigate to Nios II and click Generate. This regenerates the BSP files based on your most current compiled Intel® Quartus® Prime project settings.
    Note: Whenever you modify and recompile the Intel® Quartus® Prime project, you must regenerate the BSP files.
  7. Import the design example source (*.c) and header (*.h) files into the application directory. In the Project Explorer window, right click on the <software project> project and click Import.
  8. In the Import window, select General > File System as the import source and click Next.
  9. Browse to the <design example>/software/source directory. Check the source box on the left panel. This selects all the source and header files in the source directory. Verify that the list of source and header files are as follows:
    1. altera_jesd204_regs.h
    2. functions.h
    3. macros.h
    4. main.h
    5. macros.c
    6. main.c
  10. Verify that the destination folder is <software project>. Click Finish.
    All the source and header files should be imported into the <software project> project directory.
  11. Right-click the <software project>_bsp project, navigate to Nios II > BSP Editor . Under the Drivers tab, check the enable_small_driver box of the altera_avalon_jtag_uart_driver group and click Generate. This setting allows the compilation to proceed without connecting the interrupt ports of the JTAG UART module. After the BSP files have been generated, click Exit.
  12. Expand the <software project> application project in the Project Explorer window and verify that the folder contains all the source and header files.
  13. To compile the C code, navigate to Project > Build All.
    The compiler now compiles the C code into executable code.
  14. To download the executable code to the development board, navigate to the Run > Run Configurations. In the Run Configurations window, double-click Nios II Hardware on the left panel.
  15. Verify that all run configurations are correct, then click Run.

The Intel® Quartus® Prime software downloads the executable code onto the board and the Nios II processor executes the code. The code performs the JESD204B link initialization sequence and exits. You can view the code execution results on the Nios II Console tab. The Nios II Console is the standard input/output for the executable code. At the end of the initialization sequence, the code prints the JESD204B link status to the console. The following figure illustrates the expected result from a successful link initialization.

The following tables list the expected values of the link status register report.

Table 5.  TX Status 0 Register Expected Values
Bit Name Description Expected Binary Value
[0] SYNC_N value

0: Receiver is not in sync

1: Link is in sync

 1
[2:1] Data Link Layer (DLL) state

00: Code Group Synchronization (CGS)

01: Initial Lane Alignment Sequence (ILAS)

10: User Data Mode

11: D21.5 test mode

 10
Table 6.  RX Status 0 Register Expected Values
Bit Name Description Expected Binary Value
[0] SYNC_N value

0: Receiver is not in sync

1: Link is in sync

 1
Others N/A N/A Don’t care
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