5G LDPC Intel® FPGA IP User Guide

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ID 683107
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the 5G LDPC Intel® FPGA IP 2. Getting Started with the Intel® FPGA IP 3. Designing with the 5G LDPC Intel® FPGA IP 4. 5G LDPC Intel® FPGA IP Functional Description 5. Parameter Optimization for the 5G LDPC IP 6. 5G LDPC IP User Guide Archive 7. Document Revision History for the 5G LDPC Intel® FPGA IP User Guide
1. About the 5G LDPC Intel® FPGA IP x
1.1. 5G LDPC Intel® FPGA IP Features 1.2. 5G LDPC Intel® FPGA IP Device Family Support 1.3. 5G LDPC IP Release Information 1.4. 5G LDPC IP Performance and Resource Utilization
2. Getting Started with the Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. 5G LDPC IP IP Timeout Behavior
3. Designing with the 5G LDPC Intel® FPGA IP x
3.1. Generating a 5G LDPC Intel® FPGA IP 3.2. Simulating the 5G LDPC IP RTL 3.3. 5G LDPC Simulation Results
4. 5G LDPC Intel® FPGA IP Functional Description x
4.1. 5G LDPC Decoder 4.2. 5G LDPC Encoder 4.3. Avalon Streaming Interfaces in DSP Intel FPGA IP
4.1. 5G LDPC Decoder x
4.1.1. 5G LDPC Decoder Signals 4.1.2. 5G LDPC Decoder Data Formats 4.1.3. 5G LDPC IP Decoder Parameters
4.2. 5G LDPC Encoder x
4.2.1. 5G LDPC Encoder Signals 4.2.2. 5G LDPC Encoder Data Formats
5. Parameter Optimization for the 5G LDPC IP x
5.1. C++ and MATLAB Software Models
5.1. C++ and MATLAB Software Models x
5.1.1. Running the 5G LDPC IP C++ Models 5.1.2. Running the 5G LDPC Decoder and Encoder MATLAB Model in the Design Example
1. About the 5G LDPC Intel® FPGA IP
2. Getting Started with the Intel® FPGA IP
3. Designing with the 5G LDPC Intel® FPGA IP
4. 5G LDPC Intel® FPGA IP Functional Description
5. Parameter Optimization for the 5G LDPC IP
6. 5G LDPC IP User Guide Archive
7. Document Revision History for the 5G LDPC Intel® FPGA IP User Guide

1. About the 5G LDPC Intel® FPGA IP

Updated for:
Intel® Quartus® Prime Design Suite 24.1
IP Version 21.1.5
Low-density parity-check (LDPC) codes are linear error correcting codes that help you to transmit and receive messages over noisy channels. The 5G LDPC Intel® FPGA IP implements LDPC codes compliant with the 3rd Generation Partnership Project (3GPP) 5G specification for integration in your wireless design.

LDPC codes replace Turbo codes, popular in 3G and 4G wireless cellular communications. LDPC codes offer better spectral efficiency and support the high throughput for 5G new radio (NR).


Section Content
5G LDPC Intel FPGA IP Features
5G LDPC Intel FPGA IP Device Family Support
5G LDPC IP Release Information
5G LDPC IP Performance and Resource Utilization

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