Visible to Intel only — GUID: mwh1409958304029
Ixiasoft
1.1. IP Catalog and Parameter Editor
1.2. Installing and Licensing Intel® FPGA IP Cores
1.3. Best Practices for Intel® FPGA IP
1.4. IP General Settings
1.5. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition)
1.6. Generating IP Cores ( Intel® Quartus® Prime Standard Edition)
1.7. Modifying an IP Variation
1.8. Upgrading IP Cores
1.9. Simulating Intel® FPGA IP Cores
1.10. Synthesizing IP Cores in Other EDA Tools
1.11. Support for the IEEE 1735 Encryption Standard
1.12. Introduction to Intel® FPGA IP Cores Archives
1.13. Introduction to Intel® FPGA IP Cores Revision History
1.9.4.1.1. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts
1.9.4.1.2. Sourcing Cadence Incisive* Simulator Setup Scripts
1.9.4.1.3. Sourcing Cadence Xcelium* Simulator Setup Scripts
1.9.4.1.4. Sourcing ModelSim* or QuestaSim Simulator Setup Scripts
1.9.4.1.5. Sourcing Synopsys VCS* Simulator Setup Scripts
1.9.4.1.6. Sourcing Synopsys VCS* MX Simulator Setup Scripts
Visible to Intel only — GUID: mwh1409958304029
Ixiasoft
1.10.1. Instantiating IP Cores in HDL
Instantiate an IP core directly in your HDL code by calling the IP core name and declaring the IP core's parameters. This approach is similar to instantiating any other module, component, or subdesign. When instantiating an IP core in VHDL, you must include the associated libraries.