Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

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ID 683100
Date 2/16/2022
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Document Table of Contents
Document Table of Contents x
1. Low Latency 100G Ethernet Intel FPGA IP Overview 2. Getting Started 3. IP Core Parameters 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Registers 8. Debugging the Link 9. Ethernet Toolkit Overview 10. Low Latency 100G Ethernet Intel FPGA IP Core User Guide Archives 11. Document Revision History for the Low Latency 100G Ethernet Intel FPGA IP Core User Guide
1. Low Latency 100G Ethernet Intel FPGA IP Overview x
1.1. Low Latency 100G Ethernet Intel FPGA IP Core Supported Features 1.2. IP Core Device Family and Speed Grade Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Release Information
1.2. IP Core Device Family and Speed Grade Support x
1.2.1. Low Latency 100G Ethernet Intel FPGA IP Core Device Family Support 1.2.2. Low Latency 100G Ethernet Intel FPGA IP Core Device Speed Grade Support
1.3. IP Core Verification x
1.3.1. Simulation Environment 1.3.2. Compilation Checking 1.3.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Simulating the IP Core 2.4. Generated File Structure 2.5. Integrating Your IP Core in Your Design 2.6. IP Core Testbenches 2.7. Compiling the Full Design and Programming the FPGA
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLLs 2.5.3. Placement Settings for the Low Latency 100G Ethernet Intel FPGA IP Core
4. Functional Description x
4.1. High Level System Overview 4.2. Low Latency 100G Ethernet Intel FPGA IP Core TX Datapath 4.3. Low Latency 100G Ethernet Intel FPGA IP Core RX Datapath 4.4. Flow Control 4.5. User Interface to Ethernet Transmission 4.6. Auto Negotiation and Link Training 4.7. Auto Adaptation
4.2. Low Latency 100G Ethernet Intel FPGA IP Core TX Datapath x
4.2.1. Preamble, Start, and SFD Insertion 4.2.2. Length/Type Field Processing 4.2.3. Frame Padding 4.2.4. Frame Check Sequence (CRC-32) Insertion 4.2.5. Inter-Packet Gap Adjustment 4.2.6. Error Insertion Test and Debug Feature 4.2.7. TX PCS 4.2.8. TX RSFEC
4.3. Low Latency 100G Ethernet Intel FPGA IP Core RX Datapath x
4.3.1. Low Latency 100G Ethernet Intel FPGA IP Core Preamble Processing 4.3.2. IP Core Strict SFD Checking 4.3.3. Low Latency 100G Ethernet Intel FPGA IP Core FCS (CRC-32) Removal 4.3.4. Low Latency 100G Ethernet Intel FPGA IP Core CRC Checking 4.3.5. Low Latency 100G Ethernet Intel FPGA IP Core Malformed Packet Handling 4.3.6. RX CRC Forwarding 4.3.7. Inter-Packet Gap 4.3.8. RX PCS 4.3.9. RX RSFEC
4.4. Flow Control x
4.4.1. TX Pause/PFC Flow Control Transmission 4.4.2. XON/XOFF Pause Frames
4.5. User Interface to Ethernet Transmission x
4.5.1. Order of Transmission 4.5.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers 6.4. Transceiver Reconfiguration Signals 6.5. Avalon-MM Management Interface 6.6. Miscellaneous Status and Debug Signals 6.7. Reset Signals 6.8. Clocks 6.9. Flow Control Interface
6.4. Transceiver Reconfiguration Signals x
6.4.1. Disabling Background Calibration
7. Registers x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control Registers 7.5. Statistics Registers 7.6. TX Reed-Solomon FEC Registers 7.7. RX Reed-Solomon FEC Registers 7.8. Auto-Negotiation and Link Training Registers
7.5. Statistics Registers x
7.5.1. TX Statistics Registers 7.5.2. RX Statistics Registers
7.8. Auto-Negotiation and Link Training Registers x
7.8.1. AN/LT Sequencer Config 7.8.2. AN/LT Sequencer Status 7.8.3. Auto Negotiation Config Register 1 7.8.4. Auto Negotiation Config Register 2 7.8.5. Auto Negotiation Status Register 7.8.6. Auto Negotiation Config Register 3 7.8.7. Auto Negotiation Config Register 4 7.8.8. Auto Negotiation Config Register 5 7.8.9. Auto Negotiation Config Register 6 7.8.10. Auto Negotiation Status Register 1 7.8.11. Auto Negotiation Status Register 2 7.8.12. Auto Negotiation Status Register 3 7.8.13. Auto Negotiation Status Register 4 7.8.14. Auto Negotiation Status Register 5 7.8.15. Link Training Config Register 1 7.8.16. Link Training Config Register 2 7.8.17. Link Training Status Register 1 7.8.18. Link Training Config Register for Lane 0 7.8.19. Link Training Frame Contents for Lane 0 7.8.20. Local Transceiver TX EQ 1 Settings for Lane 0 7.8.21. Local Transceiver TX EQ 2 Settings for Lane 0 7.8.22. Local Link Training Parameters 7.8.23. Link Training Config Register for Lane 1 7.8.24. Link Training Frame Contents for Lane 1 7.8.25. Local Transceiver TX EQ 1 Settings for Lane 1 7.8.26. Local Transceiver TX EQ 2 Settings for Lane 1 7.8.27. Link Training Config Register for Lane 2 7.8.28. Link Training Frame Contents for Lane 2 Link Training Frame Contents for Lane 2 Fields 7.8.29. Local Transceiver TX EQ 1 Settings for Lane 2 7.8.30. Local Transceiver TX EQ 2 Settings for Lane 2 7.8.31. Link Training Config Register for Lane 3 7.8.32. Link Training Frame Contents for Lane 3 7.8.33. Local Transceiver TX EQ 1 Settings for Lane 3 7.8.34. Local Transceiver TX EQ 2 Settings for Lane 3
9. Ethernet Toolkit Overview x
9.1. Features
1. Low Latency 100G Ethernet Intel FPGA IP Overview
2. Getting Started
3. IP Core Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Registers
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Low Latency 100G Ethernet Intel FPGA IP Core User Guide Archives
11. Document Revision History for the Low Latency 100G Ethernet Intel FPGA IP Core User Guide

7.8.28. Link Training Frame Contents for Lane 2

Provides CSRs for the following fields that are transmitted during link training to the link partner for Lane 2
  • TX EQ Coefficient Request to Link Partner on Lane 2
  • INIT Coefficients command to Link Partner on Lane 2
  • PRESET Coefficients command to Link Partner on Lane 2
  • Local TX EQ Coefficient Status for Lane 2
  • Local Receiver Ready Status for Lane 2
  • Most Recent TX EQ Coefficient Request from Link Partner on Lane 2
  • Most Recent INIT command from Link Partner on Lane 2
  • Most Recent PRESET command from Link Partner on Lane 2
  • Most Recent TX EQ Status from Link Partner on Lane 2
  • Most Recent Receiver Ready Status from Link Partner on Lane 2

Offset: 0xE5

Access: RO and RW

Link Training Frame Contents for Lane 2 Fields

Bit Name Description Access Reset
30 lp_receiver_ready_ln2 Link Partner Receiver Ready Status for Lane 2

1: The link partner receiver has determined that training is complete and is prepared to receive data

0: The link partner receiver is requesting that training continue

RO 0x0
29:24 lp_coefficient_status_ln2 TX EQ Coefficient Status from Link Partner for Lane 2

[5:4] Status of Link Partner (+1) TX EQ Coefficient

[3:2] Status of Link Partner (0) TX EQ Coefficient

[1:0] Status of Link Partner (-1) TX EQ Coefficient

The Coefficient values are encoded as follows:
  • 2'b00: Hold
  • 2'b01: Increment
  • 2'b10: Decrement
  • 2'b11: Reserved
 RO 0x0
23 lp_preset_coefficients_ln2 PRESET Command from Link Partner on Lane 2

1: Set local TX EQ to PRESET

0: Normal Operation

This Field is normally Read-only, and the values are normally controlled by the Remote Partner Link Training SM.

When ovride_local_coef_enable=1, this field becomes writable, and is used to set the local values.

When ovride_local_coef_enable=1, use updated_local_coef_ln2=1 to write the local values.

RW 0x0
22 lp_initialize_coefficients_ln2 INIT Command from Link Partner on Lane 2

1: Set local TX EQ to INIT

0: Normal Operation

This Field is normally Read-only, and the values are normally controlled by the Remote Partner Link Training SM.

When ovride_local_coef_enable=1, this field becomes writable, and is used to set the local values.

When ovride_local_coef_enable=1, use updated_local_coef_ln2=1 to write the local values.

RW 0x0
21:16 lp_coefficient_update_ln2 TX EQ Coefficient Request from Link Partner on Lane 2

[5:4] Control for Local (+1) TX EQ Coefficient

[3:2] Control for Local (0) TX EQ Coefficient

[1:0] Control for Local (-1) TX EQ Coefficient

This Field is normally Read-only, and the values are normally controlled by the Remote Partner Link Training SM.

When ovride_local_coef_enable=1, this Field becomes writable, and is used to set the local values.

When ovride_local_coef_enable=1, use updated_local_coef_ln2=1 to write the local values.

The Coefficient values are encoded as follows:
  • 2'b00: Hold
  • 2'b01: Increment
  • 2'b10: Decrement
  • 2'b11: Reserved
 RW 0x0
14 ld_receiver_ready_ln2 Local Receiver Ready Status for Lane 2

1: The local device receiver has determined that training is complete and is prepared to receive data

0: The local device receiver is requesting that training continue

RO 0x0
13:8 ld_coefficient_status_ln2 Local TX EQ Coefficient Status for Lane 2

[5:4] Status of Local (+1) TX EQ Coefficient

[3:2] Status of Local (0) TX EQ Coefficient

[1:0] Status of Local (-1) TX EQ Coefficient

The Coefficient values are encoded as follows:
  • 2'b00: Hold
  • 2'b01: Increment
  • 2'b10: Decrement
  • 2'b11: Reserved
 RO 0x0
7 ld_preset_coefficients_ln2 PRESET Coefficients command to Link Partner on Lane 2

1: PRESET Coefficients

0: Normal Operation

This Field is normally Read-only, and the values are normally controlled by the Link Training SM.

When ovride_lp_coef_enable=1, this field becomes writable, and is used to set the values sent to the Link Partner.

When ovride_lp_coef_enable=1, useupdated_lp_coef_ln2=1 to transmit the values to the Link Partner.

The PRESET command is defined in IEEE 802.3 CL72.6.10.2.3.1.

RW 0x0
6 ld_initialize_coefficients_ln2 INIT Coefficients command to Link Partner on Lane 2

1: INIT Coefficients

0: Normal Operation

This field is normally Read-only, and the values are normally controlled by the Link Training SM.

When ovride_lp_coef_enable=1, this field becomes writable, and is used to set the values sent to the Link Partner.

When ovride_lp_coef_enable=1, useupdated_lp_coef_ln2=1 to transmit the values to the Link Partner.

The INIT command is defined in IEEE 802.3 CL72.6.10.2.3.2.

RW 0x0
5:0 ld_coefficient_update_ln2 TX EQ Coefficient Request to Link Partner on Lane 2

[5:4] Control for Link Partner (+1) TX EQ Coefficient

[3:2] Control for Link Partner (0) TX EQ Coefficient

[1:0] Control for Link Partner (-1) TX EQ Coefficient

This field is normally Read-only, and the values are normally controlled by the Link Training SM.

When ovride_lp_coef_enable=1, this field becomes writable, and is used to set the values sent to the Link Partner.

When ovride_lp_coef_enable=1, use updated_lp_coef_ln2=1 to transmit the values to the Link Partner.

The Coefficient values are encoded as follows:
  • 2'b00: Hold
  • 2'b01: Increment
  • 2'b10: Decrement
  • 2'b11: Reserved
 RW 0x0
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