Nios® V Processor Intel® FPGA IP Release Notes

Download PDF
ID 683098
Date 12/13/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Nios® V Processor Intel® FPGA IP Release Notes
1. Nios® V Processor Intel® FPGA IP Release Notes x
1.1. Nios® V/m Processor Intel® FPGA IP v21.1.1 1.2. Nios® V/m Processor Intel® FPGA IP v21.1.0
1. Nios® V Processor Intel® FPGA IP Release Notes

1.1. Nios® V/m Processor Intel® FPGA IP v21.1.1

Table 1.  v21.1.1 2021.12.13
Intel® Quartus® Prime Version Description Impact
21.4
  • Bug Fix:
    • Trigger registers accessible but triggers were not supported issue fixed.
Illegal instruction exception prompted when accessing trigger registers.
  • Added new Design Example in the Nios® V/m Processor Intel FPGA IP core parameter editor.
    • GSFI Bootloader Example Design
    • SDM Bootloader Example Design
 -
Level Two Title