Intel® Quartus® Prime Timing Analyzer Cookbook

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ID 683081
Date 7/21/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Quartus® Prime Timing Analyzer Cookbook
Intel® Quartus® Prime Timing Analyzer Cookbook x
Clocks and Generated Clocks I/O Constraints Timing Exceptions Miscellaneous Intel® Quartus® Prime Timing Analyzer Cookbook Document Revision History
Clocks and Generated Clocks x
Basic Non-50/50 Duty Cycle Clock Offset Clocks Basic Clock Divider Using -divide_by Toggle Register Generated Clock PLL Clocks Multi-Frequency Analysis
Multi-Frequency Analysis x
Clock Multiplexing Externally Switched Clock Externally Switched Clock Constraints PLL Clock Switchover
I/O Constraints x
Input and Output Delays with Virtual Clocks Tri-State Outputs System Synchronous Input System Synchronous Output I/O Timing Requirements (tSU, tH, and tCO)
Timing Exceptions x
Multicycle Exceptions False Paths
Miscellaneous x
JTAG Signals Input and Output Delays with Multiple Clocks Clock Enable Multicycle
Intel® Quartus® Prime Timing Analyzer Cookbook

Externally Switched Clock

Through an external multiplexer or jumper setting, digital systems are capable of providing different clock frequencies to the same clock port. The Timing Analyzer can model this behavior with the create_clock constraint and the -add option. The following figure shows a simple register-to-register path where you can drive the clock port clock with a 100-MHz clock or a 50-MHz clock.
Figure 8. Simple Register-to-Register Design

Externally Switched Clock Constraints

# The clk port can be driven at 100MHz (10ns) or
# 50MHz (20ns)
# clkA is 10ns
create_clock \
	-period 10.000 \
	-name clkA \
	[get_ports {clk}]
# clkB is 20ns assigned to the same port
# Requires -add option
create_clock \
	-period 20.000 \
	-name clkB \
	[get_ports {clk}] \
	-add
set_clock_groups \
	-exclusive \
	-group {clkA} \
	-group {clkB}
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