Intel® Quartus® Prime Timing Analyzer Cookbook

Download PDF
ID 683081
Date 7/21/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Quartus® Prime Timing Analyzer Cookbook
Intel® Quartus® Prime Timing Analyzer Cookbook x
Clocks and Generated Clocks I/O Constraints Timing Exceptions Miscellaneous Intel® Quartus® Prime Timing Analyzer Cookbook Document Revision History
Clocks and Generated Clocks x
Basic Non-50/50 Duty Cycle Clock Offset Clocks Basic Clock Divider Using -divide_by Toggle Register Generated Clock PLL Clocks Multi-Frequency Analysis
Multi-Frequency Analysis x
Clock Multiplexing Externally Switched Clock PLL Clock Switchover
I/O Constraints x
Input and Output Delays with Virtual Clocks Tri-State Outputs Tri-State Output Port Constraints System Synchronous Input System Synchronous Output I/O Timing Requirements (tSU, tH, and tCO)
Timing Exceptions x
Multicycle Exceptions False Paths
Miscellaneous x
JTAG Signals Input and Output Delays with Multiple Clocks Clock Enable Multicycle
Intel® Quartus® Prime Timing Analyzer Cookbook

Tri-State Outputs

Tri-state outputs allow either a valid data signal or a high impedance signal to be driven out of an output or I/O port. The timing of either signal is important in the overall system timing of the design.

The timing constraints for tri-state outputs are identical to regular output ports.

Figure 11. Typical Output Fed by a Tri-State Buffer

Tri-State Output Port Constraints

# Base clock
create_clock [get_ports {clk}] \
        -name {clk} \
        -period 10.0 \
        -waveform {0.0 5.0}
# Virtual clock for the output port
create_clock  \
        -name {clk_virt} \
        -period 10.0 \
        -waveform {0.0 5.0}
# Output constraints
set_output_delay 2.0 \
        -max \
        -clock [get_clocks {clk_virt}] \
        [get_ports {tri_out}]
set_output_delay 1.0 \
        -min \
        -clock [get_clocks {clk_virt}] \
        [get_ports {tri_out}]
Level Two Title