Intel® Quartus® Prime Timing Analyzer Cookbook

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ID 683081
Date 7/21/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Quartus® Prime Timing Analyzer Cookbook
Intel® Quartus® Prime Timing Analyzer Cookbook x
Clocks and Generated Clocks I/O Constraints Timing Exceptions Miscellaneous Intel® Quartus® Prime Timing Analyzer Cookbook Document Revision History
Clocks and Generated Clocks x
Basic Non-50/50 Duty Cycle Clock Offset Clocks Basic Clock Divider Using -divide_by Toggle Register Generated Clock PLL Clocks Multi-Frequency Analysis
Multi-Frequency Analysis x
Clock Multiplexing Externally Switched Clock PLL Clock Switchover
I/O Constraints x
Input and Output Delays with Virtual Clocks Tri-State Outputs System Synchronous Input System Synchronous Output I/O Timing Requirements (tSU, tH, and tCO)
Timing Exceptions x
Multicycle Exceptions False Paths
Miscellaneous x
JTAG Signals Input and Output Delays with Multiple Clocks Clock Enable Multicycle Clock Enable Multicycle Constraints
Intel® Quartus® Prime Timing Analyzer Cookbook

Clock Enable Multicycle

You can specify multicycles based on the enabled ports of registers with clock enabled multicycles. For example, the following figure shows a simple circuit where register enable_reg is used to create a registered enabled signal for registers din_a_reg[7..0], din_b_reg[7..0], din_x_reg[7..0], din_y_reg[7..0], a_times_b, and x_times_y.

The enable_reg register generates an enable pulse that is two times the clock period of the register. Therefore, a multicycle exception must be applied for the correct analysis. You must apply a multicycle setup of 2 and a multicycle hold of 1 to the enable-driven register fed by the register enable_reg. The multicycle exception is applied only to register-to-register paths where the destination register is controlled by enable_reg. To accomplish this, you can apply the set_multicycle_path exception to all enable-driven registers. This can be tedious, because all enable-driven registers must be specified. You can also use the combination of set_multicycle_path and get_fanouts.

Figure 18. Clock Enable Multicycle Design

Clock Enable Multicycle Constraints

#Setup multicycle of 2 to enabled driven destination registers
set_multicycle_path 2 -to [get_fanouts [get_pins enable_reg|q] \
-through [get_pins -hierarchical *|ena]] -end -setup

The target of the set_multicycle_path exception is limited to all fan-outs of the enable_reg register that feed the enable port of a register. Use the following option: 

[get_fanouts [get_pins enable_reg|q] -through [get_pins -hierarchical *|ena]]

The setup and hold relationships start at the enable_reg register and end at any enable-driven register at 2 and 1, respectively.

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