Intel® Quartus® Prime Timing Analyzer Cookbook

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ID 683081
Date 7/21/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Quartus® Prime Timing Analyzer Cookbook
Intel® Quartus® Prime Timing Analyzer Cookbook x
Clocks and Generated Clocks I/O Constraints Timing Exceptions Miscellaneous Intel® Quartus® Prime Timing Analyzer Cookbook Document Revision History
Clocks and Generated Clocks x
Basic Non-50/50 Duty Cycle Clock 60/40 Duty Cycle Clock Constraint Offset Clocks Basic Clock Divider Using -divide_by Toggle Register Generated Clock PLL Clocks Multi-Frequency Analysis
Multi-Frequency Analysis x
Clock Multiplexing Externally Switched Clock PLL Clock Switchover
I/O Constraints x
Input and Output Delays with Virtual Clocks Tri-State Outputs System Synchronous Input System Synchronous Output I/O Timing Requirements (tSU, tH, and tCO)
Timing Exceptions x
Multicycle Exceptions False Paths
Miscellaneous x
JTAG Signals Input and Output Delays with Multiple Clocks Clock Enable Multicycle
Intel® Quartus® Prime Timing Analyzer Cookbook

Basic Non-50/50 Duty Cycle Clock

The duty cycle of a clock can vary from design to design. The default duty cycle for clocks created in the Timing Analyzer is 50/50. However, you can change the duty cycle of a clock with the -waveform option.
Figure 1. Simple Register-to-Register Path with a 60/40 Duty Cycle Clock

60/40 Duty Cycle Clock Constraint

#60/40 duty cycle clock
create_clock \
	-period 10.000 \
	-waveform {0.000 6.000} \
	-name clk6040 [get_ports {clk}]
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