Intel® Quartus® Prime Standard Edition User Guide: Third-party Simulation

ID 683080
Date 11/07/2022
Public

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Document Table of Contents

2.2.53.2.15.2.2. Simulating Transport Delays2.2.53.2.15.2.2. Simulating Transport Delays2.2.53.2.15.2.2. Simulating Transport Delays

By default, the VCS and VCS MX software filter out all pulses that are shorter than the propagation delay between primitives. Turning on the transport delay options in the VCS and VCS MX software prevents the simulator from filtering out these pulses. Intel® Arria® 10 devices do not support timing simulation.

Table 7.  Table 8.  Table 11.  Transport Delay Simulation Options (VCS and VCS MX)
Option Description
+transport_path_delays Use when simulation pulses are shorter than the delay in a gate-level primitive. You must include the +pulse_e/number and +pulse_r/number options.
+transport_int_delays Use when simulation pulses are shorter than the interconnect delay between gate-level primitives. You must include the +pulse_int_e/number and +pulse_int_r/number options.
Note: The +transport_path_delays and +transport_path_delays options apply automatically during NativeLink gate-level timing simulation.

The following VCS and VCS MX software command runs a post-synthesis simulation:

vcs -R <testbench>.v <gate-level netlist>.v -v <Intel FPGA device family \
library>.v +transport_int_delays +pulse_int_e/0 +pulse_int_r/0 \
+transport_path_delays +pulse_e/0 +pulse_r/0