F-Tile Serial Lite IV Intel® FPGA IP User Guide

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ID 683074
Date 9/26/2022
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile Serial Lite IV Intel® FPGA IP User Guide 2. F-Tile Serial Lite IV Intel® FPGA IP Overview 3. Getting Started 4. Functional Description 5. Parameters 6. F-Tile Serial Lite IV Intel® FPGA IP Interface Signals 7. Designing with F-Tile Serial Lite IV Intel® FPGA IP 8. F-Tile Serial Lite IV Intel® FPGA IP User Guide Archives 9. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP User Guide
2. F-Tile Serial Lite IV Intel® FPGA IP Overview x
2.1. Release Information 2.2. Supported Features 2.3. IP Version Support Level 2.4. Device Speed Grade Support 2.5. Resource Utilization and Latency 2.6. Bandwidth Efficiency
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying the IP Parameters and Options 3.3. Generated File Structure 3.4. Simulating Intel® FPGA IP Cores 3.5. Synthesizing IP Cores in Other EDA Tools 3.6. Compiling the Full Design
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
3.4. Simulating Intel® FPGA IP Cores x
3.4.1. Simulating and Verifying the Design
4. Functional Description x
4.1. TX Datapath 4.2. RX Datapath 4.3. F-Tile Serial Lite IV Intel® FPGA IP Clock Architecture 4.4. Reset and Link Initialization 4.5. Link Rate and Bandwidth Efficiency Calculation
4.1. TX Datapath x
4.1.1. TX MAC Adapter 4.1.2. Control Word (CW) Insertion 4.1.3. TX CRC 4.1.4. TX MII Encoder 4.1.5. TX PCS and PMA
4.1.2. Control Word (CW) Insertion x
4.1.2.1. Start-of-burst CW 4.1.2.2. End-of-burst CW 4.1.2.3. Alignment Paired CW 4.1.2.4. Empty-cycle CW 4.1.2.5. Idle CW 4.1.2.6. Data Word
4.2. RX Datapath x
4.2.1. RX PCS and PMA 4.2.2. RX MII Decoder 4.2.3. RX CRC 4.2.4. RX Deskew 4.2.5. RX CW Removal
4.4. Reset and Link Initialization x
4.4.1. TX Reset and Initialization Sequence 4.4.2. RX Reset and Initialization Sequence
6. F-Tile Serial Lite IV Intel® FPGA IP Interface Signals x
6.1. Clock Signals 6.2. Reset Signals 6.3. MAC Signals 6.4. Transceiver Reconfiguration Signals 6.5. PMA Signals
7. Designing with F-Tile Serial Lite IV Intel® FPGA IP x
7.1. Reset Guidelines 7.2. Error Handling Guidelines
1. About the F-Tile Serial Lite IV Intel® FPGA IP User Guide
2. F-Tile Serial Lite IV Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. Parameters
6. F-Tile Serial Lite IV Intel® FPGA IP Interface Signals
7. Designing with F-Tile Serial Lite IV Intel® FPGA IP
8. F-Tile Serial Lite IV Intel® FPGA IP User Guide Archives
9. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP User Guide

6.1. Clock Signals

Table 23.  Clock Signals
Name Width Direction Description
tx_core_clkout 1 Output TX core clock for the TX custom PCS interface, TX MAC and user logics in the TX datapath.

This clock is generated from the custom PCS block.
rx_core_clkout 1 Output RX core clock for the RX custom PCS interface, RX deskew FIFO, RX MAC and user logics in the RX datapath.

This clock is generated from the custom PCS block.
xcvr_ref_clk 1 Input Transceiver reference clock.

When the transceiver type is set to FGT, connect this clock to the output signal (out_refclk_fgt_0) of the F-Tile Reference and System PLL Clocks Intel FPGA IP. When the transceiver type is set to FHT, connect this clock to the output signal (out_fht_cmmpll_clk_0) of the F-Tile Reference and System PLL Clocks Intel FPGA IP.

Refer to Parameters for supported frequency range.

reconfig_clk 1 Input Input clock for transceiver reconfiguration interface.

The clock frequency is 100 to 162 MHz.

Connect this input clock signal to external clock circuits or oscillators.
reconfig_sl_clk 1 Input Input clock for transceiver reconfiguration interface.

The clock frequency is 100 to 162 MHz.

Connect this input clock signal to external clock circuits or oscillators.
sysclk 1 Input System PLL clock.

Connect this clock to the output signal (out_systempll_clk_<n>) of the F-Tile Reference and System PLL Clocks Intel FPGA IP.

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