F-Tile Interlaken Intel® FPGA IP Design Example User Guide

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ID 683069
Date 9/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. F-Tile Interlaken Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for F-Tile Interlaken Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling and Configuring the Hardware Design Example 1.6. Testing the Hardware Design Example
2. Design Example Description x
2.1. Design Example Components 2.2. Analog Parameters Settings 2.3. Design Example Flow 2.4. Interface Signals 2.5. Register Map 2.6. Reset
1. Quick Start Guide
2. Design Example Description
3. F-Tile Interlaken Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for F-Tile Interlaken Intel® FPGA IP Design Example User Guide

1.2. Generating the Design

Figure 3. Procedure
Follow these steps to generate the design example and testbench:
  1. In the Quartus® Prime Pro Edition software, click File > New Project Wizard to create a new Quartus® Prime project, or click File > Open Project to open an existing Quartus® Prime project. The wizard prompts you to specify a device.
  2. Specify the device family Agilex™ 7 and select device with F-Tile for your design.
  3. In the IP Catalog, locate and double-click F-Tile Interlaken Intel FPGA IP. The New IP Variant window appears.
  4. Specify a top-level name <your_ip> for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip.
  5. Click OK. The parameter editor appears.
    Figure 4. Example Design Tab
  6. On the IP tab, specify the parameters for your IP core variation.
  7. On the Example Design tab, select the Simulation option to generate the testbench. Select the Synthesis option to generate the hardware design example. You must select at least one of the Simulation and Synthesis options to generate the design example.
  8. For Generated HDL Format, both Verilog and VHDL option is available.
  9. For Target Development Kit, select the Agilex 7 FPGA I-Series Transceiver-SoC Development Kit (4x F-Tiles).
    Note: When you select the Target Development Kit, the pin assignments are set according to the Agilex 7 FPGA I-Series Transceiver-SoC Development Kit device part number and may differ from your selected device. If you intend to test the design on hardware on a different PCB, select the None option and make the appropriate pin assignments in the .qsf file
  10. Select the Device Initialization Clock.
    The Agilex 7 FPGA I-Series Transceiver-SoC Development Kit only supports OSC_CLK_1_125MHZ
  11. Click Generate Example Design. The Select Example Design Directory window appears.
  12. If you want to modify the design example directory path or name from the defaults displayed (ilk_f_0_example_design), browse to the new path and type the new design example directory name.
  13. Click OK.
Note:
In the F-Tile Interlaken Intel FPGA IP design example, a SystemPLL is instantiated automatically, and connected to F-Tile Interlaken Intel FPGA IP. The SystemPLL hierarchy path in the design example is: 
example_design.test_env_inst.test_dut.dut.pll
The SystemPLL in the design example shares the same 156.26 MHz reference clock as the Transceiver.
Note: Very Short Reach (VSR) mode setting is added to the Design Example .qsf file to be used along with Agilex™ 7 I-Series Transceiver-SoC Development Kit. You must remove the VSR mode setting if it does not apply to your application.
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