F-Tile Interlaken Intel® FPGA IP Design Example User Guide

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ID 683069
Date 9/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. F-Tile Interlaken Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for F-Tile Interlaken Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling and Configuring the Hardware Design Example 1.6. Testing the Hardware Design Example
2. Design Example Description x
2.1. Design Example Components 2.2. Analog Parameters Settings 2.3. Design Example Flow 2.4. Interface Signals 2.5. Register Map 2.6. Reset
1. Quick Start Guide
2. Design Example Description
3. F-Tile Interlaken Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for F-Tile Interlaken Intel® FPGA IP Design Example User Guide

1.1. Hardware and Software Requirements

To test the example design, use the following hardware and software:
  • Quartus® Prime Pro Edition software
  • System console available with the Quartus® Prime Pro Edition software
  • A supported simulator:
    • Synopsys* VCS* and VCS* MX
    • Siemens* EDA QuestaSim*
    • Cadence* Xcelium*
    • Questa*-Intel® FPGA Edition
  • Agilex 7 FPGA I-Series Transceiver-SoC Development Kit (4x F-Tiles)
Level Two Title