F-Tile Interlaken Intel® FPGA IP Design Example User Guide

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ID 683069
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. F-Tile Interlaken Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for F-Tile Interlaken Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling and Configuring the Hardware Design Example 1.6. Testing the Hardware Design Example
2. Design Example Description x
2.1. Design Example Components 2.2. Analog Parameters Settings 2.3. Design Example Flow 2.4. Interface Signals 2.5. Register Map 2.6. Reset
1. Quick Start Guide
2. Design Example Description
3. F-Tile Interlaken Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for F-Tile Interlaken Intel® FPGA IP Design Example User Guide

1.3. Directory Structure

The F-Tile Interlaken Intel® FPGA IP core generates the following files for the design example:
Figure 5. Directory Structure
Table 2.  Hardware Design Example File DescriptionsThese files are in the <design_example_installation_dir>/ilk_f_0_example_design directory.
File Names Description
example_design.qpf Quartus® Prime project file.
example_design.qsf Quartus® Prime project settings file
example_design.sdc

jtag_timing_template.sdc

Synopsys* Design Constraint file. You can copy and modify for your own design.
sysconsole_testbench.tcl Main file for accessing System Console.

File location: <design_example_installation_dir>/ilk_f_0_example_design/example_design/hwtest

Table 3.  Testbench File DescriptionThis file is in the <design_example_installation_dir>/ilk_f_0_example_design/example_design/rtl directory.
File Name Description
top_tb.sv Top-level testbench file.
Table 4.  Testbench ScriptsThese files are in the <design_example_installation_dir>/ilk_f_0_example_design/example_design/testbench directory.
File Name Description
run_vcs.sh The Synopsys* VCS* script to run the testbench.
run_vcsmx.sh The Synopsys* VCS* MX script to run the testbench.
run_mentor.tcl The Siemens* EDA QuestaSim* script to run the testbench.
run_xcelium.sh The Cadence* Xcelium* script to run the testbench.
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