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2.3.1. Recommended Initial SDC Constraints
2.3.2. SDC File Precedence
2.3.3. Iterative Constraint Modification
2.3.4. Creating Clocks and Clock Constraints
2.3.5. Creating I/O Constraints
2.3.6. Creating Delay and Skew Constraints
2.3.7. Creating Timing Exceptions
2.3.8. Example Circuit and SDC File
2.3.7.5.1. Default Multicycle Analysis
2.3.7.5.2. End Multicycle Setup = 2 and End Multicycle Hold = 0
2.3.7.5.3. End Multicycle Setup = 2 and End Multicycle Hold = 1
2.3.7.5.4. Same Frequency Clocks with Destination Clock Offset
2.3.7.5.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency
2.3.7.5.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset
2.3.7.5.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency
2.3.7.5.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
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2.6. Using the Intel® Quartus® Prime Timing Analyzer Document Revision History
Document Version | Intel® Quartus® Prime Version | Changes |
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2024.02.21 | 18.1.0 |
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2018.09.24 | 18.1.0 |
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2015.11.02 | 15.1.0 |
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2015.05.04 | 15.0.0 | Added and updated contents in support of new timing algorithms for Arria 10:
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2014.12.15 | 14.1.0 | Major reorganization. Revised and added content to the following topic areas:
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August 2014 | 14.0a10.0 | Added command line compilation requirements for Arria 10 devices. |
June 2014 | 14.0.0 |
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November 2013 | 13.1.0 |
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June 2012 | 12.0.0 |
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November 2011 | 11.1.0 |
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May 2011 | 11.0.0 |
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December 2010 | 10.1.0 |
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July 2010 | 10.0.0 | Updated to link to content on SDC commands and the Timing Analyzer GUI in Intel® Quartus® Prime Help. |
November 2009 | 9.1.0 | Updated for the Intel® Quartus® Prime software version 9.1, including:
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November 2008 | 8.1.0 | Updated for the Intel® Quartus® Prime software version 8.1, including:
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