Visible to Intel only — GUID: mwh1410383757943
Ixiasoft
Visible to Intel only — GUID: mwh1410383757943
Ixiasoft
2.3.7.1. Timing Constraint Precedence
- Set False Path (set_false_path) is the first priority
- Set Minimum Delay (set_min_delay) and Set Maximum Delay (set_max_delay) are the second priority.
- Set Multicycle Path (set_multicycle_path) is the third priority.
- -from <node> is the first priority.
- -to <node> is the second priority.
- -thru <node> is the third priority.
- -from <clock> is the fourth priority.
- -to <clock> is the fifth priority.
- set_max_delay 1 -from x -to y
- set_max_delay 2 -from x
- set_max_delay 3 -to y
The first exception has higher priority than either of the other two, since the first exception specifies a -from (while #3 doesn't) and specifies a -to (while #2 doesn't). In the absence of the first exception, the second exception has higher priority than the third, since the second exception specifies a -from, which the third does not. Finally, the remaining order of precedence for additional exceptions is order-dependent, such that the assignments most recently created overwrite, or partially overwrite, earlier assignments.
- The set_net_delay exception applies regardless the existence of a set_false_path exception, or set_clock_group exception, on the same nodes.
- When targeting the Intel® Arria® 10 device or Intel® Cyclone® 10 device and using the 18.1 version of the Timing Analyzer, the set_max_skew exception applies regardless of any set_clock_group exception on the same nodes, but a set_false_path exception overrides a set_max_skew exception.