Visible to Intel only — GUID: mwh1410383666549
Ixiasoft
Visible to Intel only — GUID: mwh1410383666549
Ixiasoft
2.3.2. SDC File Precedence
Click Settings > Timing Analyzer to add, remove, or change the processing order of .sdc files in the project, as Step 3: Specify General Timing Analyzer Settings describes.
If you use the Intel® Quartus® Prime Text Editor to create an .sdc file, the option to Add file to the project enables by default when you save the file. If you use any other editor to create an .sdc file, you must add the file to the project.
The .sdc file must contain only timing constraint commands. Tcl commands to manipulate the timing netlist or control the compilation must be in a separate Tcl script.
When you use IP from Intel, and some third-parties, the .sdc files become part of the project through an intermediate Intel® Quartus® Prime IP File (.qip). The .qip file references all source and constraints files for the IP. If .sdc files for IP blocks in your design are included through with a .qip, do not re-add them manually. An .sdc file can also be added from a Intel® Quartus® Prime IP File (.qip) included in the .qsf.