Intel® Quartus® Prime Standard Edition User Guide: Timing Analyzer

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ID 683068
Date 2/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Timing Analysis Introduction 2. Using the Intel® Quartus® Prime Timing Analyzer A. Intel® Quartus® Prime Standard Edition User Guides
1. Timing Analysis Introduction x
1.1. Timing Analysis Basic Concepts 1.2. Document Revision History
1.1. Timing Analysis Basic Concepts x
1.1.1. Timing Path and Clock Analysis 1.1.2. Clock Setup Analysis 1.1.3. Clock Hold Analysis 1.1.4. Recovery and Removal Analysis 1.1.5. Multicycle Path Analysis 1.1.6. Metastability Analysis 1.1.7. Timing Pessimism 1.1.8. Clock-As-Data Analysis 1.1.9. Multicorner Analysis
1.1.1. Timing Path and Clock Analysis x
1.1.1.1. The Timing Netlist 1.1.1.2. Timing Paths 1.1.1.3. Data and Clock Arrival Times 1.1.1.4. Launch and Latch Edges
1.1.5. Multicycle Path Analysis x
1.1.5.1. Multicycle Clock Hold 1.1.5.2. Multicycle Clock Setup
2. Using the Intel® Quartus® Prime Timing Analyzer x
2.1. Enhanced Timing Analysis for Intel® Arria® 10 Devices 2.2. Basic Timing Analysis Flow 2.3. Using Timing Constraints 2.4. Timing Analyzer Tcl Commands 2.5. Timing Analysis of Imported Compilation Results 2.6. Using the Intel® Quartus® Prime Timing Analyzer Document Revision History
2.2. Basic Timing Analysis Flow x
2.2.1. Step 1: Open a Project and Run the Fitter 2.2.2. Step 2: Specify Timing Constraints 2.2.3. Step 3: Specify General Timing Analyzer Settings 2.2.4. Step 4: Run Timing Analysis 2.2.5. Step 5: Analyze Timing Analysis Results
2.2.5. Step 5: Analyze Timing Analysis Results x
2.2.5.1. Timing Report Commands 2.2.5.2. Set Operating Conditions 2.2.5.3. Fmax Summary Report 2.2.5.4. Report Timing Command 2.2.5.5. Correlating Constraints to the Timing Report 2.2.5.6. Locating Timing Paths in Other Tools
2.3. Using Timing Constraints x
2.3.1. Recommended Initial SDC Constraints 2.3.2. SDC File Precedence 2.3.3. Iterative Constraint Modification 2.3.4. Creating Clocks and Clock Constraints 2.3.5. Creating I/O Constraints 2.3.6. Creating Delay and Skew Constraints 2.3.7. Creating Timing Exceptions 2.3.8. Example Circuit and SDC File
2.3.1. Recommended Initial SDC Constraints x
2.3.1.1. Create Clock (create_clock) 2.3.1.2. Derive PLL Clocks (derive_pll_clocks) 2.3.1.3. Derive Clock Uncertainty (derive_clock_uncertainty) 2.3.1.4. Set Clock Groups (set_clock_groups)
2.3.4. Creating Clocks and Clock Constraints x
2.3.4.1. Creating Base Clocks 2.3.4.2. Creating Virtual Clocks 2.3.4.3. Creating Generated Clocks (create_generated_clock) 2.3.4.4. Deriving PLL Clocks 2.3.4.5. Creating Clock Groups (set_clock_groups) 2.3.4.6. Accounting for Clock Effect Characteristics
2.3.4.1. Creating Base Clocks x
2.3.4.1.1. Automatic Clock Detection and Constraint Creation
2.3.4.2. Creating Virtual Clocks x
2.3.4.2.1. Specifying I/O Interface Uncertainty 2.3.4.2.2. I/O Interface Clock Uncertainty Example
2.3.4.3. Creating Generated Clocks (create_generated_clock) x
2.3.4.3.1. Clock Divider Example (-divide_by) 2.3.4.3.2. Clock Multiplexor Example
2.3.4.5. Creating Clock Groups (set_clock_groups) x
2.3.4.5.1. Exclusive Clock Groups (-exclusive) 2.3.4.5.2. Asynchronous Clock Groups (-asynchronous) 2.3.4.5.3. set_clock_groups Constraint Tips
2.3.4.6. Accounting for Clock Effect Characteristics x
2.3.4.6.1. Set Clock Latency (set_clock_latency) 2.3.4.6.2. Clock Uncertainty
2.3.5. Creating I/O Constraints x
2.3.5.1. Input Constraints (set_input_delay) 2.3.5.2. Output Constraints (set_output_delay)
2.3.6. Creating Delay and Skew Constraints x
2.3.6.1. Advanced I/O Timing and Board Trace Model Delay 2.3.6.2. Maximum Skew (set_max_skew) 2.3.6.3. Net Delay (set_net_delay) 2.3.6.4. Create Timing Netlist
2.3.7. Creating Timing Exceptions x
2.3.7.1. Timing Constraint Precedence 2.3.7.2. False Paths (set_false_path) 2.3.7.3. Minimum and Maximum Delays 2.3.7.4. Multicycle Paths 2.3.7.5. Multicycle Exception Examples 2.3.7.6. Delay Annotation
2.3.7.4. Multicycle Paths x
2.3.7.4.1. Common Multicycle Applications 2.3.7.4.2. Relaxing Setup with Multicycle (set_multicyle_path) 2.3.7.4.3. Accounting for a Phase Shift (-phase)
2.3.7.5. Multicycle Exception Examples x
2.3.7.5.1. Default Multicycle Analysis 2.3.7.5.2. End Multicycle Setup = 2 and End Multicycle Hold = 0 2.3.7.5.3. End Multicycle Setup = 2 and End Multicycle Hold = 1 2.3.7.5.4. Same Frequency Clocks with Destination Clock Offset 2.3.7.5.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency 2.3.7.5.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset 2.3.7.5.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency 2.3.7.5.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
2.4. Timing Analyzer Tcl Commands x
2.4.1. The quartus_sta Executable 2.4.2. Collection Commands 2.4.3. Identifying the Intel® Quartus® Prime Software Executable from the SDC File
2.4.2. Collection Commands x
2.4.2.1. Wildcard Characters 2.4.2.2. Adding and Removing Collection Items 2.4.2.3. Query of Collections 2.4.2.4. Using the get_pins Command
1. Timing Analysis Introduction
2. Using the Intel® Quartus® Prime Timing Analyzer
A. Intel® Quartus® Prime Standard Edition User Guides

2.3.6.2. Maximum Skew (set_max_skew)

The Set Max Skew (set_max_skew) constraint specifies the maximum allowable skew between the sets of registers or ports or ports you specify. In order to constrain skew across multiple paths, you must constrain all such paths within a single set_max_skew constraint. 
set_max_skew -from_clock { clock } -to_clock { * } -from foo -to blat 2

The set_max_delay, set_min_delay, and set_multicycle_path do not affect set_max_skew timing constraints for this 18.1 version of the Timing Analyzer. However, set_false_path and set_clock_groups do impact set_max_skew. If your design targets an Intel® Arria® 10 device or Intel® Cyclone® 10 device, set_clock_groups does not affect set_max_skew constraints.

Table 12.  set_max_skew Options
Arguments Description
-h | -help Short help.
-long_help Long help with examples and possible return values.
-exclude <Tcl list> A Tcl list of parameters to exclude during skew analysis. This list includes one or more of the following: utsu, uth, utco, from_clock, to_clock, clock_uncertainty, ccpp, input_delay, output_delay, odv.
Note: Intel® Arria® 10 devices do no support this argument.
-fall_from_clock <names> Valid source clocks (Tcl matches string patterns).
names> Valid destination clocks (Tcl matches string patterns).
-from <-fall_to_clock <names> 1 Valid sources (Tcl matches string patterns).
-fall_to_clock -from_clock <names> Valid source clocks (Tcl matches string patterns).
-get_skew_value_from_clock_period <src_clock_period|dst_clock_period|min_clock_period> Option to interpret skew constraint as a multiple of the clock period.
-include <Tcl list> Tcl list of parameters to include during skew analysis. This list can include one or more of the following: utsu, uth, utco, from_clock, to_clock, clock_uncertainty, ccpp, input_delay, output_delay, odv.
Note: Intel® Arria® 10 devices do not support this argument .
-rise_from_clock <names> Valid source clocks (Tcl matches string patterns).
-rise_to_clock <names> Valid destination clocks (Tcl matches string patterns).
-skew_value_multiplier <multiplier> Value by which the clock period multiplies to compute skew requirement.
-to <names> 1 Valid destinations (Tcl matches string patterns)
-to_clock <names> Valid destination clocks (Tcl matches string patterns).
<skew> Skew you require.

Applying maximum skew constraints between clocks applies the constraint from all register or ports driven by the clock you specify (with the -from option) to all registers or ports driven by the clock you specify (with the -to option).

Use the -include and -exclude options to include or exclude one or more of the following: register micro parameters (utsu, uth, utco), clock arrival times (from_clock, to_clock), clock uncertainty (clock_uncertainty), common clock path pessimism removal (ccpp), input and output delays (input_delay, output_delay) and on-die variation (odv).

Max skew analysis can include data arrival times, clock arrival times, register micro parameters, clock uncertainty, on-die variation, and ccpp removal. Among these, only ccpp removal disables during the Fitter by default. When you use -include , the default analysis includes those in the inclusion list. Similarly, if you use -exclude, the default analysis excludes those in the exclusion list. When both the -include and -exclude options specify the same parameter, that parameter is excluded.

Note: If your design targets an Intel® Arria® 10 device, -exclude and -include are not supported.

Use -get_skew_value_from_clock_period to set the skew as a multiple of the launching or latching clock period, or whichever of the two has a smaller period. If you use this option, set -skew_value_multiplier, and you may not set the positional skew option. If more than one clock clocks the set of skew paths, Timing Analyzer uses the clock with smallest period to compute the skew constraint.

Click Report Max Skew (report_max_skew) to view the max skew analysis. Since skew occurs between two or more paths, no results display if the -from/-from_clock and -to/-to_clock filters satisfy less than two paths.

1 Legal values for the -from and -to options are collections of clocks, registers, ports, pins, cells or partitions in a design.
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