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2.3.1. Recommended Initial SDC Constraints
2.3.2. SDC File Precedence
2.3.3. Iterative Constraint Modification
2.3.4. Creating Clocks and Clock Constraints
2.3.5. Creating I/O Constraints
2.3.6. Creating Delay and Skew Constraints
2.3.7. Creating Timing Exceptions
2.3.8. Example Circuit and SDC File
2.3.7.5.1. Default Multicycle Analysis
2.3.7.5.2. End Multicycle Setup = 2 and End Multicycle Hold = 0
2.3.7.5.3. End Multicycle Setup = 2 and End Multicycle Hold = 1
2.3.7.5.4. Same Frequency Clocks with Destination Clock Offset
2.3.7.5.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency
2.3.7.5.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset
2.3.7.5.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency
2.3.7.5.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
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2.4.3. Identifying the Intel® Quartus® Prime Software Executable from the SDC File
To identify which Intel® Quartus® Prime software executable is currently running you can use the $::TimingAnalyzerInfo(nameofexecutable) variable from within an SDC file. This technique is most commonly used when you want to use an overconstraint to cause the Fitter to work harder on a particular path or set of paths in the design.
Identifying the Intel® Quartus® Prime Executable
#Identify which executable is running: set current_exe $::TimingAnalyzerInfo(nameofexecutable) if { [string equal $current_exe "quartus_fit"] } { #Apply .sdc assignments for Fitter executable here } else { #Apply .sdc assignments for non-Fitter executables here } if { ! [string equal "quartus_sta" $::TimingAnalyzerInfo(nameofexecutable)] } { #Apply .sdc assignments for non-Timing Analyzer executables here } else { #Apply .sdc assignments for Timing Analyzer executable here }
Examples of different executable names are quartus_map for Analysis & Synthesis, quartus_fit for Fitter, and quartus_sta for the Timing Analyzer.