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2.3.1. Recommended Initial SDC Constraints
2.3.2. SDC File Precedence
2.3.3. Iterative Constraint Modification
2.3.4. Creating Clocks and Clock Constraints
2.3.5. Creating I/O Constraints
2.3.6. Creating Delay and Skew Constraints
2.3.7. Creating Timing Exceptions
2.3.8. Example Circuit and SDC File
2.3.7.5.1. Default Multicycle Analysis
2.3.7.5.2. End Multicycle Setup = 2 and End Multicycle Hold = 0
2.3.7.5.3. End Multicycle Setup = 2 and End Multicycle Hold = 1
2.3.7.5.4. Same Frequency Clocks with Destination Clock Offset
2.3.7.5.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency
2.3.7.5.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset
2.3.7.5.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency
2.3.7.5.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
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2.3.4.3.2. Clock Multiplexor Example
The output of a clock multiplexor (mux) is a form of generated clock. Each input clock requires one generated clock on the output. The following .sdc example also includes the set_clock_groups command to indicate that the two generated clocks can never be active simultaneously in the design. Therefore, the Timing Analyzer does not analyze cross-domain paths between the generated clocks on the output of the clock mux.
Figure 49. Clock Mux
create_clock -name clock_a -period 10 [get_ports clk_a] create_clock -name clock_b -period 10 [get_ports clk_b] create_generated_clock -name clock_a_mux -source [get_ports clk_a] \ [get_pins clk_mux|mux_out] create_generated_clock -name clock_b_mux -source [get_ports clk_b] \ [get_pins clk_mux|mux_out] -add set_clock_groups -exclusive -group clock_a_mux -group clock_b_mux