Intel® Quartus® Prime Standard Edition User Guide: Timing Analyzer

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ID 683068
Date 2/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Timing Analysis Introduction 2. Using the Intel® Quartus® Prime Timing Analyzer A. Intel® Quartus® Prime Standard Edition User Guides
1. Timing Analysis Introduction x
1.1. Timing Analysis Basic Concepts 1.2. Document Revision History
1.1. Timing Analysis Basic Concepts x
1.1.1. Timing Path and Clock Analysis 1.1.2. Clock Setup Analysis 1.1.3. Clock Hold Analysis 1.1.4. Recovery and Removal Analysis 1.1.5. Multicycle Path Analysis 1.1.6. Metastability Analysis 1.1.7. Timing Pessimism 1.1.8. Clock-As-Data Analysis 1.1.9. Multicorner Analysis
1.1.1. Timing Path and Clock Analysis x
1.1.1.1. The Timing Netlist 1.1.1.2. Timing Paths 1.1.1.3. Data and Clock Arrival Times 1.1.1.4. Launch and Latch Edges
1.1.5. Multicycle Path Analysis x
1.1.5.1. Multicycle Clock Hold 1.1.5.2. Multicycle Clock Setup
2. Using the Intel® Quartus® Prime Timing Analyzer x
2.1. Enhanced Timing Analysis for Intel® Arria® 10 Devices 2.2. Basic Timing Analysis Flow 2.3. Using Timing Constraints 2.4. Timing Analyzer Tcl Commands 2.5. Timing Analysis of Imported Compilation Results 2.6. Using the Intel® Quartus® Prime Timing Analyzer Document Revision History
2.2. Basic Timing Analysis Flow x
2.2.1. Step 1: Open a Project and Run the Fitter 2.2.2. Step 2: Specify Timing Constraints 2.2.3. Step 3: Specify General Timing Analyzer Settings 2.2.4. Step 4: Run Timing Analysis 2.2.5. Step 5: Analyze Timing Analysis Results
2.2.5. Step 5: Analyze Timing Analysis Results x
2.2.5.1. Timing Report Commands 2.2.5.2. Set Operating Conditions 2.2.5.3. Fmax Summary Report 2.2.5.4. Report Timing Command 2.2.5.5. Correlating Constraints to the Timing Report 2.2.5.6. Locating Timing Paths in Other Tools
2.3. Using Timing Constraints x
2.3.1. Recommended Initial SDC Constraints 2.3.2. SDC File Precedence 2.3.3. Iterative Constraint Modification 2.3.4. Creating Clocks and Clock Constraints 2.3.5. Creating I/O Constraints 2.3.6. Creating Delay and Skew Constraints 2.3.7. Creating Timing Exceptions 2.3.8. Example Circuit and SDC File
2.3.1. Recommended Initial SDC Constraints x
2.3.1.1. Create Clock (create_clock) 2.3.1.2. Derive PLL Clocks (derive_pll_clocks) 2.3.1.3. Derive Clock Uncertainty (derive_clock_uncertainty) 2.3.1.4. Set Clock Groups (set_clock_groups)
2.3.4. Creating Clocks and Clock Constraints x
2.3.4.1. Creating Base Clocks 2.3.4.2. Creating Virtual Clocks 2.3.4.3. Creating Generated Clocks (create_generated_clock) 2.3.4.4. Deriving PLL Clocks 2.3.4.5. Creating Clock Groups (set_clock_groups) 2.3.4.6. Accounting for Clock Effect Characteristics
2.3.4.1. Creating Base Clocks x
2.3.4.1.1. Automatic Clock Detection and Constraint Creation
2.3.4.2. Creating Virtual Clocks x
2.3.4.2.1. Specifying I/O Interface Uncertainty 2.3.4.2.2. I/O Interface Clock Uncertainty Example
2.3.4.3. Creating Generated Clocks (create_generated_clock) x
2.3.4.3.1. Clock Divider Example (-divide_by) 2.3.4.3.2. Clock Multiplexor Example
2.3.4.5. Creating Clock Groups (set_clock_groups) x
2.3.4.5.1. Exclusive Clock Groups (-exclusive) 2.3.4.5.2. Asynchronous Clock Groups (-asynchronous) 2.3.4.5.3. set_clock_groups Constraint Tips
2.3.4.6. Accounting for Clock Effect Characteristics x
2.3.4.6.1. Set Clock Latency (set_clock_latency) 2.3.4.6.2. Clock Uncertainty
2.3.5. Creating I/O Constraints x
2.3.5.1. Input Constraints (set_input_delay) 2.3.5.2. Output Constraints (set_output_delay)
2.3.6. Creating Delay and Skew Constraints x
2.3.6.1. Advanced I/O Timing and Board Trace Model Delay 2.3.6.2. Maximum Skew (set_max_skew) 2.3.6.3. Net Delay (set_net_delay) 2.3.6.4. Create Timing Netlist
2.3.7. Creating Timing Exceptions x
2.3.7.1. Timing Constraint Precedence 2.3.7.2. False Paths (set_false_path) 2.3.7.3. Minimum and Maximum Delays 2.3.7.4. Multicycle Paths 2.3.7.5. Multicycle Exception Examples 2.3.7.6. Delay Annotation
2.3.7.4. Multicycle Paths x
2.3.7.4.1. Common Multicycle Applications 2.3.7.4.2. Relaxing Setup with Multicycle (set_multicyle_path) 2.3.7.4.3. Accounting for a Phase Shift (-phase)
2.3.7.5. Multicycle Exception Examples x
2.3.7.5.1. Default Multicycle Analysis 2.3.7.5.2. End Multicycle Setup = 2 and End Multicycle Hold = 0 2.3.7.5.3. End Multicycle Setup = 2 and End Multicycle Hold = 1 2.3.7.5.4. Same Frequency Clocks with Destination Clock Offset 2.3.7.5.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency 2.3.7.5.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset 2.3.7.5.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency 2.3.7.5.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
2.4. Timing Analyzer Tcl Commands x
2.4.1. The quartus_sta Executable 2.4.2. Collection Commands 2.4.3. Identifying the Intel® Quartus® Prime Software Executable from the SDC File
2.4.2. Collection Commands x
2.4.2.1. Wildcard Characters 2.4.2.2. Adding and Removing Collection Items 2.4.2.3. Query of Collections 2.4.2.4. Using the get_pins Command
1. Timing Analysis Introduction
2. Using the Intel® Quartus® Prime Timing Analyzer
A. Intel® Quartus® Prime Standard Edition User Guides

1.1.8. Clock-As-Data Analysis

The majority of FPGA designs contain simple connections between any two nodes known as either a data path or a clock path.

A data path is a connection between the output of a synchronous element to the input of another synchronous element.

A clock is a connection to the clock pin of a synchronous element. However, for more complex FPGA designs, such as designs that use source-synchronous interfaces, this simplified view is no longer sufficient. Clock-as-data analysis is performed in circuits with elements such as clock dividers and DDR source-synchronous outputs.

The connection between the input clock port and output clock port can be treated either as a clock path or a data path. A design where the path from port clk_in to port clk_out is both a clock and a data path. The clock path is from the port clk_in to the register reg_data clock pin. The data path is from port clk_in to the port clk_out.

Figure 32. Simplified Source Synchronous Output

With clock-as-data analysis, the Timing Analyzer provides a more accurate analysis of the path based on user constraints. For the clock path analysis, any phase shift associated with the phase-locked loop (PLL) is taken into consideration. For the data path analysis, any phase shift associated with the PLL is taken into consideration rather than ignored.

The clock-as-data analysis also applies to internally generated clock dividers. An internally generated clock divider. In this figure, waveforms are for the inverter feedback path, analyzed during timing analysis. The output of the divider register is used to determine the launch time and the clock port of the register is used to determine the latch time.

Figure 33. Clock Divider
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