Integer Arithmetic Intel® FPGA IP Cores Release Notes

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ID 683061
Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
1. Integer Arithmetic IP Cores Release Notes
1. Integer Arithmetic IP Cores Release Notes x
1.1. Multiply Adder Intel FPGA IP 1.2. ALTMULT_COMPLEX Intel FPGA IP 1.3. LPM_MULT Intel FPGA IP 1.4. LPM_DIVIDE Intel FPGA IP 1.5. ALTMEMMULT IP 1.6. Stratix® 10 Variable Precision DSP Blocks User Guide Document Archives 1.7. MAX® 10 Embedded Multipliers User Guide Archives 1.8. Integer Arithmetic Intel® FPGA IP Cores User Guide Document Archives
1.1. Multiply Adder Intel FPGA IP x
1.1.1. Multiply Adder Intel FPGA IP v19.2.1 1.1.2. Multiply Adder Intel FPGA IP v19.1.0 1.1.3. Multiply Adder Intel FPGA IP Core v18.0 1.1.4. Intel FPGA Multiply Adder v17.1 1.1.5. ALTMULT_ADD IP Core v17.0 1.1.6. ALTERA_MULT_ADD IP Core v16.0
1.2. ALTMULT_COMPLEX Intel FPGA IP x
1.2.1. ALTMULT_COMPLEX Intel FPGA IP v19.1.0 1.2.2. ALTMULT_COMPLEX Intel FPGA IP Core v18.0 1.2.3. ALTMULT_COMPLEX IP Core v17.1 1.2.4. ALTMULT_COMPLEX IP Core v17.0 1.2.5. ALTMULT_COMPLEX IP Core v16.0
1.3. LPM_MULT Intel FPGA IP x
1.3.1. LPM_MULT Intel FPGA IP v19.2.1 1.3.2. LPM_MULT Intel FPGA IP v19.1.0 1.3.3. LPM_MULT Intel FPGA IP Core v18.0 1.3.4. LPM_MULT IP Core v17.1 1.3.5. LPM_MULT IP Core v17.0 1.3.6. LPM_MULT IP Core v16.0
1.4. LPM_DIVIDE Intel FPGA IP x
1.4.1. LPM_DIVIDE Intel FPGA IP v19.1
1.5. ALTMEMMULT IP x
1.5.1. ALTMEMMULT IP v19.1.0
1. Integer Arithmetic IP Cores Release Notes

1.3.6. LPM_MULT IP Core v16.0

Table 20.  v16.0 May 2016
Description Impact
  • Added synchronous clear signal support for output pipeline register for Arria 10 devices.
  • Replaced Create an asynchronous Clear input checkbox with Clear Signal Type drop down box with the values of NONE, ACLR, and SCLR in the IP parameter editor for users selection. This change is only applicable to Arria 10 devices.
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