Integer Arithmetic Intel® FPGA IP Cores Release Notes

Download PDF
ID 683061
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Integer Arithmetic IP Cores Release Notes
1. Integer Arithmetic IP Cores Release Notes x
1.1. Multiply Adder Intel FPGA IP 1.2. ALTMULT_COMPLEX Intel FPGA IP 1.3. LPM_MULT Intel FPGA IP 1.4. LPM_DIVIDE Intel FPGA IP 1.5. ALTMEMMULT IP 1.6. Stratix® 10 Variable Precision DSP Blocks User Guide Document Archives 1.7. MAX® 10 Embedded Multipliers User Guide Archives 1.8. Integer Arithmetic Intel® FPGA IP Cores User Guide Document Archives
1.1. Multiply Adder Intel FPGA IP x
1.1.1. Multiply Adder Intel FPGA IP v19.2.1 1.1.2. Multiply Adder Intel FPGA IP v19.1.0 1.1.3. Multiply Adder Intel FPGA IP Core v18.0 1.1.4. Intel FPGA Multiply Adder v17.1 1.1.5. ALTMULT_ADD IP Core v17.0 1.1.6. ALTERA_MULT_ADD IP Core v16.0
1.2. ALTMULT_COMPLEX Intel FPGA IP x
1.2.1. ALTMULT_COMPLEX Intel FPGA IP v19.1.0 1.2.2. ALTMULT_COMPLEX Intel FPGA IP Core v18.0 1.2.3. ALTMULT_COMPLEX IP Core v17.1 1.2.4. ALTMULT_COMPLEX IP Core v17.0 1.2.5. ALTMULT_COMPLEX IP Core v16.0
1.3. LPM_MULT Intel FPGA IP x
1.3.1. LPM_MULT Intel FPGA IP v19.2.1 1.3.2. LPM_MULT Intel FPGA IP v19.1.0 1.3.3. LPM_MULT Intel FPGA IP Core v18.0 1.3.4. LPM_MULT IP Core v17.1 1.3.5. LPM_MULT IP Core v17.0 1.3.6. LPM_MULT IP Core v16.0
1.4. LPM_DIVIDE Intel FPGA IP x
1.4.1. LPM_DIVIDE Intel FPGA IP v19.1
1.5. ALTMEMMULT IP x
1.5.1. ALTMEMMULT IP v19.1.0
1. Integer Arithmetic IP Cores Release Notes

1. Integer Arithmetic IP Cores Release Notes

If a release note is not available for a specific IP version, the IP has no changes in that version. For information on IP update releases up to v18.1, refer to the Quartus® Prime Design Suite Update Release Notes.

Intel® FPGA IP versions match the Quartus® Prime Design Suite software versions until v19.1. Starting in Quartus® Prime Design Suite software version 19.2, Intel® FPGA IP has a new versioning scheme.

The Intel® FPGA IP version (X.Y.Z) number can change with each Quartus® Prime software version. A change in:

  • X indicates a major revision of the IP. If you update the Quartus® Prime software, you must regenerate the IP.
  • Y indicates the IP includes new features. Regenerate your IP to include these new features.
  • Z indicates the IP includes minor changes. Regenerate your IP to include these changes.

Section Content
Multiply Adder Intel FPGA IP
ALTMULT_COMPLEX Intel FPGA IP
LPM_MULT Intel FPGA IP
LPM_DIVIDE Intel FPGA IP
ALTMEMMULT IP
Stratix 10 Variable Precision DSP Blocks User Guide Document Archives
MAX 10 Embedded Multipliers User Guide Archives
Integer Arithmetic Intel FPGA IP Cores User Guide Document Archives

Related Information
Level Two Title