AN 759: Using Secure Boot in Intel® Arria® 10 SoC Devices

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ID 683060
Date 3/29/2021
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Document Table of Contents
Document Table of Contents x
AN 759: Using Secure Boot in Intel® Arria® 10 SoC Devices
AN 759: Using Secure Boot in Intel® Arria® 10 SoC Devices x
Prerequisites References Secure Boot Stages Intel® Arria® 10 SoC Secure Boot Architecture Software Image Authentication Overview of the Secure Boot Flow Software Image Encryption Software Image Authentication and Encryption Intel® Arria® 10 SoC FPGA Authentication Signing Utility Secure Boot Examples Appendix A: Secure Boot Image Python Script: alt_authtool.py Appendix B: Frequently Asked Questions Document Revision History for the AN 759: Using Secure Boot in Intel® Arria® 10 SoC Devices
Secure Boot Stages x
Root of Trust First-Stage Boot Loader (ROM) Second-Stage Boot Loader Third and Fourth Stages
Software Image Authentication x
Digital Signing Root of Trust and Root Key Authentication of the Second-Stage Boot Loader Security Level Staging Signed Image Root Key Types Root Public Key Authentication Test Secure Boot Authentication Programming the Secure Signing Key Generating the Signing Key Pair with OpenSSL
Programming the Secure Signing Key x
Boot Image Signing Flow Boot Image Authentication
Overview of the Secure Boot Flow x
Creating a Secure Boot System
Software Image Encryption x
AES Encryption and Decryption Encrypting the Boot Image and Configuration File Boot Image Encryption Flow Programming the AES Encryption Key
Intel® Arria® 10 SoC FPGA Authentication Signing Utility x
Secure Boot Image Tool Boot Image Format Tool
Secure Boot Examples x
Prerequisites Creating a Signed First-Stage Boot Loader Image Creating an Encrypted First-Stage Boot Loader Image Creating a Signed and Encrypted First-Stage Boot Loader Image
Appendix B: Frequently Asked Questions x
What are the secure configurations for HPS JTAG debug and access? Can the HPS perform decryption of the boot image instead of the FPGA CSS? What happens if the first stage boot ROM is unsuccessful in authenticating the second-stage boot loader? Can you use the first-stage root key as the subsequent stage root key? When the second-stage image is authenticated, is the image header only copied to on-chip RAM for authentication? Can the AES encryption key be updated by the HPS using JTAG hosting? How does U-Boot (SSBL) authenticate next stage boot images? Which elliptical cryptography is used for boot image signing and authentication? How do I generate a signing key pair? Where can I store the signing keys for second-stage boot loader authentication? What type of cryptography is used for boot image encryption and decryption? What FPGA locations are available for AES key storage? How do I generate an AES key to encrypt a boot image? How is secure boot defined within the Intel® Arria® 10 SoC product family? What security choices are available for the second-stage boot image or user software? Where is the authentication of the boot image performed? Where is decryption of the boot image performed? How can I configure the Intel® Arria® 10 SoC device so that it always performs authentication or authentication and decryption? How can I program the key authentication key (KAK) into the Intel® Arria® 10 SoC device? How can I configure the second stage boot loader image for the correct authentication signing key type? How do I configure the second-stage boot loader image for encryption using the pre-generated AES key? Is the ECDSA private and public key pair that is used for signing the boot image also used for authentication of the FPGA image?
AN 759: Using Secure Boot in Intel® Arria® 10 SoC Devices

AN 759: Using Secure Boot in Intel® Arria® 10 SoC Devices

Updated for:
Intel® Quartus® Prime Design Suite 20.4

The Intel® Arria® 10 SoC device family and supported tools provide features and resources to create a secure boot system. Secure booting is essential to protect the design's intellectual property (through encryption) and prevent malicious software from running on the system (through authentication). A secure boot system establishes a chain of trust. Each piece of firmware or software is validated before running, and also validates the security signature on the next piece of software before loading it for execution.

This document provides methods and design examples for implementing an Intel® Arria® 10 SoC secure boot system using tools from the Intel® Arria® 10 SoC FPGA Authentication Signing Utility to secure the first-stage boot loader image. It shows how to generate a secure boot loader, creating and programming secure keys for image authentication and image encryption and decryption.

Note: Securing boot stages after the second-stage boot loader is outside the scope of this document and is dependent on your choice of OS and application. If the boot loader must secure subsequent boot stages (such as the operating system), you must implement a secure boot flow at the second-stage boot loader. Intel® Arria® 10 SoC FPGA Authentication Signing Utility does not provide any specific support for boot security beyond the second-stage boot loader.
Note: This document reflects information available at the time of publication. To ensure that you have the most recent information about enhancements to the tools and tool flow, refer to the Intel® Arria® 10 SoC FPGA Authentication Signing Utility.
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