Visible to Intel only — GUID: jhl1486507390281
Ixiasoft
Visible to Intel only — GUID: jhl1486507390281
Ixiasoft
4.5.1. User-Coded Reset Controller Signals
Signal Name |
Direction |
Description |
---|---|---|
pll_powerdown | Output |
Resets the TX PLL when asserted high. |
tx_analogreset | Output |
Resets the TX PMA when asserted high. |
tx_digitalreset | Output |
Resets the TX PCS when asserted high. |
rx_analogreset | Output |
Resets the RX PMA when asserted high. |
rx_digitalreset | Output |
Resets the RX PCS when asserted high. |
clock | Input |
Clock signal for the user-coded reset controller. You can use the system clock without synchronizing it to the PHY parallel clock. The upper limit on the input clock frequency is the frequency achieved in timing closure. |
pll_cal_busy | Input |
A high on this signal indicates the PLL is being calibrated. |
pll_locked | Input |
A high on this signal indicates that the TX PLL is locked to the ref clock. |
tx_cal_busy | Input |
A high on this signal indicates that TX calibration is active. If you have multiple PLLs, you can OR their pll_cal_busy signals together. |
rx_is_lockedtodata | Input |
A high on this signal indicates that the RX CDR is in the lock-to-data (LTD) mode. |
rx_cal_busy | Input |
A high on this signal indicates that RX calibration is active. |
rx_is_lockedtoref | Input |
A high on this signal indicates that the RX CDR is in the lock-to-reference (LTR) mode. This signal may toggle or be deasserted when the CDR is in LTD mode. |