Intel® Cyclone® 10 GX Transceiver PHY User Guide

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ID 683054
Date 4/14/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Cyclone® 10 GX Transceiver PHY Overview 2. Implementing Protocols in Intel® Cyclone® 10 GX Transceivers 3. PLLs and Clock Networks 4. Resetting Transceiver Channels 5. Cyclone® 10 GX Transceiver PHY Architecture 6. Reconfiguration Interface and Dynamic Reconfiguration 7. Calibration 8. Analog Parameter Settings
1. Intel® Cyclone® 10 GX Transceiver PHY Overview x
1.1. Device Transceiver Layout 1.2. Transceiver PHY Architecture Overview 1.3. Calibration 1.4. Intel® Cyclone® 10 GX Transceiver PHY Overview Revision History
1.1. Device Transceiver Layout x
1.1.1. Intel® Cyclone® 10 GX Device Transceiver Layout 1.1.2. Intel® Cyclone® 10 GX Device Package Details
1.2. Transceiver PHY Architecture Overview x
1.2.1. Transceiver Bank Architecture 1.2.2. PHY Layer Transceiver Components 1.2.3. Transceiver Phase-Locked Loops 1.2.4. Clock Generation Block (CGB)
1.2.2. PHY Layer Transceiver Components x
1.2.2.1. The Transceiver Channel
1.2.3. Transceiver Phase-Locked Loops x
1.2.3.1. Advanced Transmit (ATX) PLL 1.2.3.2. Fractional PLL (fPLL) 1.2.3.3. Channel PLL (CMU/CDR PLL)
2. Implementing Protocols in Intel® Cyclone® 10 GX Transceivers x
2.1. Transceiver Design IP Blocks 2.2. Transceiver Design Flow 2.3. Cyclone® 10 GX Transceiver Protocols and PHY IP Support 2.4. Using the Cyclone® 10 GX Transceiver Native PHY IP Core 2.5. Interlaken 2.6. Ethernet 2.7. PCI Express (PIPE) 2.8. CPRI 2.9. Other Protocols 2.10. Simulating the Transceiver Native PHY IP Core 2.11. Implementing Protocols in Intel® Cyclone® 10 GX Transceivers Revision History
2.2. Transceiver Design Flow x
2.2.1. Select and Instantiate the PHY IP Core 2.2.2. Configure the PHY IP Core 2.2.3. Generate the PHY IP Core 2.2.4. Select the PLL IP Core 2.2.5. Configure the PLL IP Core 2.2.6. Generate the PLL IP Core 2.2.7. Reset Controller 2.2.8. Create Reconfiguration Logic 2.2.9. Connect the PHY IP to the PLL IP Core and Reset Controller 2.2.10. Connect Datapath 2.2.11. Make Analog Parameter Settings 2.2.12. Compile the Design 2.2.13. Verify Design Functionality
2.4. Using the Cyclone® 10 GX Transceiver Native PHY IP Core x
2.4.1. Presets 2.4.2. General and Datapath Parameters 2.4.3. PMA Parameters 2.4.4. Enhanced PCS Parameters 2.4.5. Standard PCS Parameters 2.4.6. PCS Direct 2.4.7. Dynamic Reconfiguration Parameters 2.4.8. PMA Ports 2.4.9. Enhanced PCS Ports 2.4.10. Standard PCS Ports 2.4.11. IP Core File Locations 2.4.12. Unused Transceiver Channels
2.4.9. Enhanced PCS Ports x
2.4.9.1. Enhanced PCS TX and RX Control Ports
2.5. Interlaken x
2.5.1. Metaframe Format and Framing Layer Control Word 2.5.2. Interlaken Configuration Clocking and Bonding 2.5.3. How to Implement Interlaken in Cyclone® 10 GX Transceivers 2.5.4. Native PHY IP Parameter Settings for Interlaken
2.5.2. Interlaken Configuration Clocking and Bonding x
2.5.2.1. xN Clock Bonding Scenario 2.5.2.2. TX Multi-Lane Bonding and RX Multi-Lane Deskew Alignment State Machine
2.5.2.2. TX Multi-Lane Bonding and RX Multi-Lane Deskew Alignment State Machine x
2.5.2.2.1. TX FIFO Soft Bonding 2.5.2.2.2. RX Multi-lane FIFO Deskew State Machine
2.6. Ethernet x
2.6.1. Gigabit Ethernet (GbE) and GbE with IEEE 1588v2 2.6.2. 10GBASE-R and 10GBASE-R with IEEE 1588v2 Variants 2.6.3. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core 2.6.4. Acronyms
2.6.1. Gigabit Ethernet (GbE) and GbE with IEEE 1588v2 x
2.6.1.1. 8B/10B Encoding for GbE, GbE with IEEE 1588v2 2.6.1.2. Word Alignment for GbE, GbE with IEEE 1588v2 2.6.1.3. 8B/10B Decoding for GbE, GbE with IEEE 1588v2 2.6.1.4. Rate Match FIFO for GbE 2.6.1.5. How to Implement GbE, GbE with IEEE 1588v2 in Intel® Cyclone® 10 GX Transceivers 2.6.1.6. Native PHY IP Parameter Settings for GbE and GbE with IEEE 1588v2
2.6.1.1. 8B/10B Encoding for GbE, GbE with IEEE 1588v2 x
2.6.1.1.1. Reset Condition for 8B/10B Encoder in GbE, GbE with IEEE 1588v2
2.6.2. 10GBASE-R and 10GBASE-R with IEEE 1588v2 Variants x
2.6.2.1. The XGMII Clocking Scheme in 10GBASE-R 2.6.2.2. How to Implement 10GBASE-R and 10GBASE-R with IEEE 1588v2 in Intel® Cyclone® 10 GX Transceivers 2.6.2.3. Native PHY IP Parameter Settings for 10GBASE-R and 10GBASE-R with IEEE 1588v2 2.6.2.4. Native PHY IP Ports for 10GBASE-R and 10GBASE-R with IEEE 1588v2 Transceiver Configurations
2.6.2.1. The XGMII Clocking Scheme in 10GBASE-R x
2.6.2.1.1. TX FIFO and RX FIFO
2.6.3. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core x
2.6.3.1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core 2.6.3.2. Using the IP Core 2.6.3.3. Functional Description 2.6.3.4. Configuration Registers 2.6.3.5. Interface Signals
2.6.3.1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core x
2.6.3.1.1. Features 2.6.3.1.2. Release Information 2.6.3.1.3. Device Family Support 2.6.3.1.4. Resource Utilization
2.6.3.2. Using the IP Core x
2.6.3.2.1. Parameter Settings
2.6.3.3. Functional Description x
2.6.3.3.1. Clocking and Reset Sequence 2.6.3.3.2. Timing Constraints 2.6.3.3.3. Switching Operation Speed
2.6.3.5. Interface Signals x
2.6.3.5.1. Clock and Reset Signals 2.6.3.5.2. Operating Mode and Speed Signals 2.6.3.5.3. XGMII Signals 2.6.3.5.4. Status Signals 2.6.3.5.5. Serial Interface Signals 2.6.3.5.6. Transceiver Status and Reconfiguration Signals 2.6.3.5.7. Avalon® Memory-Mapped Interface Signals
2.7. PCI Express (PIPE) x
2.7.1. Transceiver Channel Datapath for PIPE 2.7.2. Supported PIPE Features 2.7.3. How to Connect TX PLLs for PIPE Gen1 and Gen2 Modes 2.7.4. How to Implement PCI Express (PIPE) in Cyclone® 10 GX Transceivers 2.7.5. Native PHY IP Parameter Settings for PIPE 2.7.6. fPLL IP Parameter Core Settings for PIPE 2.7.7. ATX PLL IP Parameter Core Settings for PIPE 2.7.8. Native PHY IP Ports for PIPE 2.7.9. fPLL Ports for PIPE 2.7.10. ATX PLL Ports for PIPE 2.7.11. How to Place Channels for PIPE Configurations
2.7.2. Supported PIPE Features x
2.7.2.1. Gen1/Gen2 Features
2.7.2.1. Gen1/Gen2 Features x
2.7.2.1.1. Dynamic Switching Between Gen1 (2.5 Gbps) and Gen2 (5 Gbps) 2.7.2.1.2. Transmitter Electrical Idle Generation 2.7.2.1.3. Power State Management 2.7.2.1.4. 8B/10B Encoder Usage for Compliance Pattern Transmission Support 2.7.2.1.5. Receiver Status 2.7.2.1.6. Receiver Detection 2.7.2.1.7. Gen1 and Gen2 Clock Compensation 2.7.2.1.8. PCIe Reverse Parallel Loopback
2.7.11. How to Place Channels for PIPE Configurations x
2.7.11.1. Master Channel in Bonded Configurations
2.8. CPRI x
2.8.1. Transceiver Channel Datapath and Clocking for CPRI 2.8.2. Supported Features for CPRI 2.8.3. Word Aligner in Manual Mode for CPRI 2.8.4. How to Implement CPRI in Cyclone® 10 GX Transceivers 2.8.5. Native PHY IP Parameter Settings for CPRI
2.8.1. Transceiver Channel Datapath and Clocking for CPRI x
2.8.1.1. TX PLL Selection for CPRI 2.8.1.2. Auto-Negotiation
2.8.2. Supported Features for CPRI x
2.8.2.1. Word Aligner in Deterministic Latency Mode for CPRI
2.8.2.1. Word Aligner in Deterministic Latency Mode for CPRI x
2.8.2.1.1. Transmitter and Receiver Latency
2.9. Other Protocols x
2.9.1. Using the 'Basic (Enhanced PCS)' Configuration 2.9.2. Using the Basic/Custom, Basic/Custom with Rate Match Configurations of Standard PCS 2.9.3. How to Implement PCS Direct Transceiver Configuration Rule
2.9.1. Using the 'Basic (Enhanced PCS)' Configuration x
2.9.1.1. How to Implement the Basic (Enhanced PCS) Transceiver Configuration Rules in Cyclone® 10 GX Transceivers 2.9.1.2. Native PHY IP Parameter Settings for Basic (Enhanced PCS) 2.9.1.3. How to Enable Low Latency in Basic Enhanced PCS 2.9.1.4. Enhanced PCS FIFO Operation 2.9.1.5. TX Data Bitslip 2.9.1.6. TX Data Polarity Inversion 2.9.1.7. RX Data Bitslip 2.9.1.8. RX Data Polarity Inversion
2.9.2. Using the Basic/Custom, Basic/Custom with Rate Match Configurations of Standard PCS x
2.9.2.1. Word Aligner Manual Mode 2.9.2.2. Word Aligner Synchronous State Machine Mode 2.9.2.3. RX Bit Slip 2.9.2.4. RX Polarity Inversion 2.9.2.5. RX Bit Reversal 2.9.2.6. RX Byte Reversal 2.9.2.7. Rate Match FIFO in Basic (Single Width) Mode 2.9.2.8. Rate Match FIFO Basic (Double Width) Mode 2.9.2.9. 8B/10B Encoder and Decoder 2.9.2.10. 8B/10B TX Disparity Control 2.9.2.11. How to Enable Low Latency in Basic 2.9.2.12. TX Bit Slip 2.9.2.13. TX Polarity Inversion 2.9.2.14. TX Bit Reversal 2.9.2.15. TX Byte Reversal 2.9.2.16. How to Implement the Basic, Basic with Rate Match Transceiver Configuration Rules in Cyclone® 10 GX Transceivers 2.9.2.17. Native PHY IP Parameter Settings for Basic, Basic with Rate Match Configurations
2.10. Simulating the Transceiver Native PHY IP Core x
2.10.1. NativeLink Simulation Flow 2.10.2. Scripting IP Simulation 2.10.3. Custom Simulation Flow
2.10.1. NativeLink Simulation Flow x
2.10.1.1. How to Use NativeLink to Specify a ModelSim Simulation 2.10.1.2. How to Use NativeLink to Run a ModelSim RTL Simulation 2.10.1.3. How to Use NativeLink to Specify Third-Party RTL Simulators
2.10.2. Scripting IP Simulation x
2.10.2.1. Generating a Combined Simulator Setup Script
2.10.3. Custom Simulation Flow x
2.10.3.1. How to Use the Simulation Library Compiler 2.10.3.2. Custom Simulation Scripts
3. PLLs and Clock Networks x
3.1. PLLs 3.2. Input Reference Clock Sources 3.3. Transmitter Clock Network 3.4. Clock Generation Block 3.5. FPGA Fabric-Transceiver Interface Clocking 3.6. Transmitter Data Path Interface Clocking 3.7. Receiver Data Path Interface Clocking 3.8. Unused/Idle Clock Line Requirements 3.9. Channel Bonding 3.10. PLL Feedback and Cascading Clock Network 3.11. Using PLLs and Clock Networks 3.12. PLLs and Clock Networks Revision History
3.1. PLLs x
3.1.1. Transmit PLLs Spacing Guidelines when using ATX PLLs and fPLLs 3.1.2. ATX PLL 3.1.3. fPLL 3.1.4. CMU PLL
3.1.2. ATX PLL x
3.1.2.1. Instantiating the ATX PLL IP Core 3.1.2.2. ATX PLL IP Core
3.1.3. fPLL x
3.1.3.1. Instantiating the fPLL IP Core 3.1.3.2. fPLL IP Core
3.1.4. CMU PLL x
3.1.4.1. Instantiating CMU PLL IP Core 3.1.4.2. CMU PLL IP Core
3.2. Input Reference Clock Sources x
3.2.1. Dedicated Reference Clock Pins 3.2.2. Receiver Input Pins 3.2.3. PLL Cascading as an Input Reference Clock Source 3.2.4. Reference Clock Network 3.2.5. Global Clock or Core Clock as an Input Reference Clock
3.3. Transmitter Clock Network x
3.3.1. x1 Clock Lines 3.3.2. x6 Clock Lines 3.3.3. xN Clock Lines
3.9. Channel Bonding x
3.9.1. PMA Bonding 3.9.2. PMA and PCS Bonding 3.9.3. Selecting Channel Bonding Schemes 3.9.4. Skew Calculations
3.9.1. PMA Bonding x
3.9.1.1. x6/xN Bonding 3.9.1.2. PLL Feedback Compensation Bonding
3.11. Using PLLs and Clock Networks x
3.11.1. Non-bonded Configurations 3.11.2. Bonded Configurations 3.11.3. Implementing PLL Cascading 3.11.4. Timing Closure Recommendations
3.11.1. Non-bonded Configurations x
3.11.1.1. Implementing Single Channel x1 Non-Bonded Configuration 3.11.1.2. Implementing Multi-Channel x1 Non-Bonded Configuration 3.11.1.3. Implementing Multi-Channel xN Non-Bonded Configuration
3.11.2. Bonded Configurations x
3.11.2.1. Implementing x6/xN Bonding Mode 3.11.2.2. Implementing PLL Feedback Compensation Bonding Mode
4. Resetting Transceiver Channels x
4.1. When Is Reset Required? 4.2. Transceiver PHY Implementation 4.3. How Do I Reset? 4.4. Using the Transceiver PHY Reset Controller 4.5. Using a User-Coded Reset Controller 4.6. Combining Status or PLL Lock Signals 4.7. Timing Constraints for Bonded PCS and PMA Channels 4.8. Resetting Transceiver Channels Revision History
4.3. How Do I Reset? x
4.3.1. Model 1: Default Model 4.3.2. Model 2: Acknowledgment Model 4.3.3. Transceiver Blocks Affected by Reset and Powerdown Signals
4.3.1. Model 1: Default Model x
4.3.1.1. Recommended Reset Sequence 4.3.1.2. Resetting the Transmitter During Device Operation 4.3.1.3. Resetting the Receiver During Device Operation 4.3.1.4. Resetting the Transceiver Channel During Device Operation 4.3.1.5. Dynamic Reconfiguration of Channel Using the Default Model
4.3.1.3. Resetting the Receiver During Device Operation x
4.3.1.3.1. Clock Data Recovery in Auto Lock Mode 4.3.1.3.2. Clock Data Recovery in Manual Lock Mode 4.3.1.3.3. Control Settings for CDR Manual Lock Mode 4.3.1.3.4. Resetting the Transceiver in CDR Manual Lock Mode
4.3.2. Model 2: Acknowledgment Model x
4.3.2.1. Recommended Reset Sequence 4.3.2.2. Resetting the Transmitter During Device Operation 4.3.2.3. Resetting the Receiver During Device Operation 4.3.2.4. Dynamic Reconfiguration of Transmitter Channel Using the Acknowledgment Model 4.3.2.5. Dynamic Reconfiguration of Receiver Channel Using the Acknowledgment Model
4.4. Using the Transceiver PHY Reset Controller x
4.4.1. Parameterizing the Transceiver PHY Reset Controller IP 4.4.2. Transceiver PHY Reset Controller Parameters 4.4.3. Transceiver PHY Reset Controller Interfaces Usage Examples for pll_select 4.4.4. Transceiver PHY Reset Controller Resource Utilization
4.5. Using a User-Coded Reset Controller x
4.5.1. User-Coded Reset Controller Signals
5. Cyclone® 10 GX Transceiver PHY Architecture x
5.1. Cyclone® 10 GX PMA Architecture 5.2. Cyclone® 10 GX Enhanced PCS Architecture 5.3. Cyclone® 10 GX Standard PCS Architecture 5.4. Intel® Cyclone® 10 GX Transceiver PHY Architecture Revision History
5.1. Cyclone® 10 GX PMA Architecture x
5.1.1. Transmitter 5.1.2. Serializer 5.1.3. Transmitter Buffer 5.1.4. Receiver 5.1.5. Receiver Buffer 5.1.6. Clock Data Recovery (CDR) Unit 5.1.7. Deserializer 5.1.8. Loopback
5.1.3. Transmitter Buffer x
5.1.3.1. High Speed Differential I/O 5.1.3.2. Programmable Output Differential Voltage 5.1.3.3. Programmable Pre-Emphasis 5.1.3.4. Power Distribution Network (PDN) induced Inter-Symbol Interference (ISI) compensation 5.1.3.5. Programmable Transmitter On-Chip Termination (OCT)
5.1.5. Receiver Buffer x
5.1.5.1. Programmable Common Mode Voltage (VCM) 5.1.5.2. Programmable Differential On-Chip Termination (OCT) 5.1.5.3. Signal Detector 5.1.5.4. Continuous Time Linear Equalization (CTLE) 5.1.5.5. Variable Gain Amplifier (VGA) 5.1.5.6. How to Enable CTLE
5.1.5.4. Continuous Time Linear Equalization (CTLE) x
5.1.5.4.1. High Gain Mode
5.1.5.6. How to Enable CTLE x
5.1.5.6.1. Configuration Methods
5.1.6. Clock Data Recovery (CDR) Unit x
5.1.6.1. Lock-to-Reference Mode 5.1.6.2. Lock-to-Data Mode 5.1.6.3. CDR Lock Modes
5.1.6.3. CDR Lock Modes x
5.1.6.3.1. Automatic Lock Mode 5.1.6.3.2. Manual Lock Mode
5.2. Cyclone® 10 GX Enhanced PCS Architecture x
5.2.1. Transmitter Datapath 5.2.2. Receiver Datapath
5.2.1. Transmitter Datapath x
5.2.1.1. Enhanced PCS TX FIFO 5.2.1.2. Interlaken Frame Generator 5.2.1.3. Interlaken CRC-32 Generator 5.2.1.4. 64B/66B Encoder and Transmitter State Machine (TX SM) 5.2.1.5. Pattern Generators 5.2.1.6. Scrambler 5.2.1.7. Interlaken Disparity Generator 5.2.1.8. TX Gearbox, TX Bitslip and Polarity Inversion
5.2.1.1. Enhanced PCS TX FIFO x
5.2.1.1.1. Phase Compensation Mode 5.2.1.1.2. Register Mode 5.2.1.1.3. Interlaken Mode 5.2.1.1.4. Basic Mode
5.2.1.5. Pattern Generators x
5.2.1.5.1. PRBS Pattern Generator (Shared between Enhanced PCS and Standard PCS) 5.2.1.5.2. Pseudo-Random Pattern Generator
5.2.2. Receiver Datapath x
5.2.2.1. RX Gearbox, RX Bitslip, and Polarity Inversion 5.2.2.2. Block Synchronizer 5.2.2.3. Interlaken Disparity Checker 5.2.2.4. Descrambler 5.2.2.5. Interlaken Frame Synchronizer 5.2.2.6. 64B/66B Decoder and Receiver State Machine (RX SM) 5.2.2.7. Pseudo Random Pattern Verifier 5.2.2.8. 10GBASE-R Bit-Error Rate (BER) Checker 5.2.2.9. Interlaken CRC-32 Checker 5.2.2.10. Enhanced PCS RX FIFO
5.2.2.6. 64B/66B Decoder and Receiver State Machine (RX SM) x
5.2.2.6.1. PRBS Checker
5.2.2.10. Enhanced PCS RX FIFO x
5.2.2.10.1. Phase Compensation Mode 5.2.2.10.2. Register Mode 5.2.2.10.3. Interlaken Mode 5.2.2.10.4. 10GBASE-R Mode 5.2.2.10.5. Idle OS Deletion 5.2.2.10.6. Idle Insertion 5.2.2.10.7. Basic Mode
5.3. Cyclone® 10 GX Standard PCS Architecture x
5.3.1. Transmitter Datapath 5.3.2. Receiver Datapath
5.3.1. Transmitter Datapath x
5.3.1.1. TX FIFO (Shared with Enhanced PCS and PCIe Gen2 PCS) 5.3.1.2. Byte Serializer 5.3.1.3. 8B/10B Encoder 5.3.1.4. Polarity Inversion Feature 5.3.1.5. Pseudo-Random Binary Sequence (PRBS) Generator 5.3.1.6. TX Bit Slip
5.3.1.1. TX FIFO (Shared with Enhanced PCS and PCIe Gen2 PCS) x
5.3.1.1.1. TX FIFO Low Latency Mode 5.3.1.1.2. TX FIFO Register Mode 5.3.1.1.3. TX FIFO Fast Register Mode
5.3.1.2. Byte Serializer x
5.3.1.2.1. Bonded Byte Serializer 5.3.1.2.2. Byte Serializer Disabled Mode 5.3.1.2.3. Byte Serializer Serialize x2 Mode 5.3.1.2.4. Byte Serializer Serialize x4 Mode
5.3.1.3. 8B/10B Encoder x
5.3.1.3.1. 8B/10B Encoder Control Code Encoding 5.3.1.3.2. 8B/10B Encoder Reset Condition 5.3.1.3.3. 8B/10B Encoder Idle Character Replacement Feature 5.3.1.3.4. 8B/10B Encoder Current Running Disparity Control Feature 5.3.1.3.5. 8B/10B Encoder Bit Reversal Feature 5.3.1.3.6. 8B/10B Encoder Byte Reversal Feature
5.3.2. Receiver Datapath x
5.3.2.1. Word Aligner 5.3.2.2. RX Polarity Inversion Feature 5.3.2.3. Rate Match FIFO 5.3.2.4. 8B/10B Decoder 5.3.2.5. Pseudo-Random Binary Sequence (PRBS) Checker 5.3.2.6. Byte Deserializer 5.3.2.7. RX FIFO (Shared with Enhanced PCS and PCIe Gen2 PCS)
5.3.2.1. Word Aligner x
5.3.2.1.1. Word Aligner Bit Slip Mode 5.3.2.1.2. Word Aligner Manual Mode 5.3.2.1.3. Word Aligner Synchronous State Machine Mode 5.3.2.1.4. Word Aligner Deterministic Latency Mode 5.3.2.1.5. Word Aligner Pattern Length for Various Word Aligner Modes 5.3.2.1.6. Word Aligner RX Bit Reversal Feature 5.3.2.1.7. Word Aligner RX Byte Reversal Feature
5.3.2.4. 8B/10B Decoder x
5.3.2.4.1. 8B/10B Decoder Control Code Encoding 5.3.2.4.2. 8B/10B Decoder Running Disparity Checker Feature
5.3.2.6. Byte Deserializer x
5.3.2.6.1. Byte Deserializer Disabled Mode 5.3.2.6.2. Byte Deserializer Deserialize x2 Mode 5.3.2.6.3. Byte Deserializer Deserialize x4 Mode 5.3.2.6.4. Bonded Byte Deserializer
5.3.2.7. RX FIFO (Shared with Enhanced PCS and PCIe Gen2 PCS) x
5.3.2.7.1. RX FIFO Low Latency Mode 5.3.2.7.2. RX FIFO Register Mode
6. Reconfiguration Interface and Dynamic Reconfiguration x
6.1. Reconfiguring Channel and PLL Blocks 6.2. Interacting with the Reconfiguration Interface 6.3. Configuration Files 6.4. Multiple Reconfiguration Profiles 6.5. Embedded Reconfiguration Streamer 6.6. Arbitration 6.7. Recommendations for Dynamic Reconfiguration 6.8. Steps to Perform Dynamic Reconfiguration 6.9. Direct Reconfiguration Flow 6.10. Native PHY IP or PLL IP Core Guided Reconfiguration Flow 6.11. Reconfiguration Flow for Special Cases 6.12. Changing PMA Analog Parameters 6.13. Ports and Parameters 6.14. Dynamic Reconfiguration Interface Merging Across Multiple IP Blocks 6.15. Embedded Debug Features 6.16. Using Data Pattern Generators and Checkers 6.17. Timing Closure Recommendations 6.18. Unsupported Features 6.19. Cyclone® 10 GX Transceiver Register Map 6.20. Reconfiguration Interface and Dynamic Reconfiguration Revision History
6.2. Interacting with the Reconfiguration Interface x
6.2.1. Reading from the Reconfiguration Interface 6.2.2. Writing to the Reconfiguration Interface
6.11. Reconfiguration Flow for Special Cases x
6.11.1. Switching Transmitter PLL 6.11.2. Switching Reference Clocks
6.11.2. Switching Reference Clocks x
6.11.2.1. ATX Reference Clock Switching 6.11.2.2. fPLL Reference Clock Switching 6.11.2.3. CDR and CMU Reference Clock Switching
6.12. Changing PMA Analog Parameters x
6.12.1. Changing VOD, Pre-emphasis Using Direct Reconfiguration Flow 6.12.2. Changing CTLE Settings in Manual Mode Using Direct Reconfiguration Flow 6.12.3. Enabling and Disabling Loopback Modes Using Direct Reconfiguration Flow
6.15. Embedded Debug Features x
6.15.1. Native PHY Debug Master Endpoint 6.15.2. Optional Reconfiguration Logic
6.15.2. Optional Reconfiguration Logic x
6.15.2.1. Capability Registers 6.15.2.2. Control and Status Registers 6.15.2.3. PRBS Soft Accumulators
6.16. Using Data Pattern Generators and Checkers x
6.16.1. Using PRBS Data Pattern Generator and Checker 6.16.2. Using Pseudo Random Pattern Mode
6.16.1. Using PRBS Data Pattern Generator and Checker x
6.16.1.1. Enabling the PRBS Data Generator in Non Bonded designs 6.16.1.2. Enabling the PRBS Data Generator in Bonded Designs 6.16.1.3. Enabling the PRBS Data Checker in Non Bonded design 6.16.1.4. Enabling the PRBS Checker in bonded designs 6.16.1.5. Disabling/Enabling PRBS Pattern Inversion
6.16.1.1. Enabling the PRBS Data Generator in Non Bonded designs x
6.16.1.1.1. Examples of Enabling the PRBS9 and PRBS31 Pattern Generators in Non Bonded designs
6.16.1.2. Enabling the PRBS Data Generator in Bonded Designs x
6.16.1.2.1. Examples of Enabling the PRBS9 and PRBS31 Pattern Generators in Bonded Designs
6.16.1.3. Enabling the PRBS Data Checker in Non Bonded design x
6.16.1.3.1. Examples of Enabling the PRBS Data Checker
6.16.2. Using Pseudo Random Pattern Mode x
6.16.2.1. Enabling Pseudo Random Pattern Mode
7. Calibration x
7.1. Reconfiguration Interface and Arbitration with PreSICE Calibration Engine 7.2. Calibration Registers 7.3. Power-up Calibration 7.4. User Recalibration 7.5. Calibration Example 7.6. Calibration Revision History
7.2. Calibration Registers x
7.2.1. Avalon® Memory-Mapped Interface Arbitration Registers 7.2.2. Transceiver Channel Calibration Registers 7.2.3. Fractional PLL Calibration Registers 7.2.4. ATX PLL Calibration Registers 7.2.5. Capability Registers 7.2.6. Rate Switch Flag Register
7.2.5. Capability Registers x
7.2.5.1. Rules to Build Customized Gating Logic to Separate tx_cal_busy and rx_cal_busy signals 7.2.5.2. PMA Capability Registers for Calibration Status
7.4. User Recalibration x
7.4.1. Conditions That Require User Recalibration 7.4.2. User Recalibration Sequence
7.5. Calibration Example x
7.5.1. ATX PLL Recalibration 7.5.2. Fractional PLL Recalibration 7.5.3. CDR/CMU PLL Recalibration 7.5.4. PMA Recalibration
8. Analog Parameter Settings x
8.1. Making Analog Parameter Settings using the Assignment Editor 8.2. Updating Quartus Settings File with the Known Assignment 8.3. Analog Parameter Settings List 8.4. Receiver General Analog Settings 8.5. Receiver Analog Equalization Settings 8.6. Transmitter General Analog Settings 8.7. Transmitter Pre-Emphasis Analog Settings 8.8. Transmitter VOD Settings 8.9. Dedicated Reference Clock Settings 8.10. Unused Transceiver Channels Settings 8.11. Analog Parameter Settings Revision History
8.4. Receiver General Analog Settings x
8.4.1. XCVR_C10_RX_TERM_SEL
8.5. Receiver Analog Equalization Settings x
8.5.1. CTLE Settings 8.5.2. VGA Settings
8.5.1. CTLE Settings x
8.5.1.1. XCVR_C10_RX_ONE_STAGE_ENABLE 8.5.1.2. XCVR_C10_RX_EQ_DC_GAIN_TRIM 8.5.1.3. XCVR_C10_RX_ADP_CTLE_ACGAIN_4S 8.5.1.4. XCVR_C10_RX_ADP_CTLE_EQZ_1S_SEL
8.5.2. VGA Settings x
8.5.2.1. XCVR_C10_RX_ADP_VGA_SEL
8.6. Transmitter General Analog Settings x
8.6.1. XCVR_C10_TX_TERM_SEL 8.6.2. XCVR_C10_TX_COMPENSATION_EN 8.6.3. XCVR_C10_TX_SLEW_RATE_CTRL
8.7. Transmitter Pre-Emphasis Analog Settings x
8.7.1. XCVR_C10_TX_PRE_EMP_SIGN_PRE_TAP_1T 8.7.2. XCVR_C10_TX_PRE_EMP_SIGN_PRE_TAP_2T 8.7.3. XCVR_C10_TX_PRE_EMP_SIGN_1ST_POST_TAP 8.7.4. XCVR_C10_TX_PRE_EMP_SIGN_2ND_POST_TAP 8.7.5. XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T 8.7.6. XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T 8.7.7. XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 8.7.8. XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP
8.8. Transmitter VOD Settings x
8.8.1. XCVR_C10_TX_VOD_OUTPUT_SWING_CTRL
8.9. Dedicated Reference Clock Settings x
8.9.1. XCVR_C10_REFCLK_TERM_TRISTATE 8.9.2. XCVR_C10_TX_XTX_PATH_ANALOG_MODE
1. Intel® Cyclone® 10 GX Transceiver PHY Overview
2. Implementing Protocols in Intel® Cyclone® 10 GX Transceivers
3. PLLs and Clock Networks
4. Resetting Transceiver Channels
5. Cyclone® 10 GX Transceiver PHY Architecture
6. Reconfiguration Interface and Dynamic Reconfiguration
7. Calibration
8. Analog Parameter Settings

4.4.3. Transceiver PHY Reset Controller Interfaces

This section describes the top-level signals for the Transceiver PHY Reset Controller IP core.

The following figure illustrates the top-level signals of the Transceiver PHY Reset Controller IP core. Many of the signals in the figure become buses if you choose separate reset controls. The variables in the figure represent the following parameters:

  • <n>—The number of lanes
  • <p>—The number of PLLs
Figure 162. Transceiver PHY Reset Controller IP Core Top-Level SignalsGenerating the IP core creates signals and ports based on your parameter settings.


Note: PLL control is available when you enable the Expose Port parameter.
Table 173.  Top-Level SignalsThis table describes the signals in the above figure in the order that they are shown in the figure.
Signal Name Direction Clock Domain Description
pll_locked[<p>-1:0] Input Asynchronous Provides the PLL locked status input from each PLL. When asserted, indicates that the TX PLL is locked. When deasserted, the PLL is not locked. There is one signal per PLL.
pll_select[<p*n>-1:0] Input Synchronous to the Transceiver PHY Reset Controller input clock. Set to zero when not using multiple PLLs. When you select Use separate TX reset per channel, this bus provides enough inputs to specify an index for each pll_locked signal to listen to for each channel. When Use separate TX reset per channel is disabled, the pll_select signal is used for all channels.

n=1 when a single TX reset sequence is used for all channels.

tx_cal_busy[<n> -1:0] Input Asynchronous

This is the calibration status signal that results from the logical OR of pll_cal_busy and tx_cal_busy signals. The signal goes high when either the TX PLL or Transceiver PHY initial calibration is active. It is not asserted if you manually re-trigger the calibration IP. The signal goes low when calibration is completed. This signal gates the TX reset sequence. The width of this signals depends on the number of TX channels.

rx_cal_busy[<n> -1:0] Input Asynchronous This is calibration status signal from the Transceiver PHY IP core. When asserted, the initial calibration is active. When deasserted, calibration has completed. It is not asserted if you manually re-trigger the calibration IP. This signal gates the RX reset sequence. The width of this signals depends on the number of RX channels.
rx_is_lockedtodata [<n>-1:0] Input Synchronous to CDR Provides the rx_is_lockedtodata status from each RX CDR. When asserted, indicates that a particular RX CDR is ready to receive input data. If you do not choose separate controls for the RX channels, these inputs are ANDed together internally to provide a single status signal.
tx_manual[<n>-1:0] Input Asynchronous This optional signal places tx_digitalreset controller under automatic or manual control. When asserted, the associated tx_digitalreset controller logic does not automatically respond to deassertion of the pll_locked signal. However, the initial tx_digitalreset sequence still requires a one-time rising edge on pll_locked before proceeding. When deasserted, the associated tx_digitalreset controller automatically begins its reset sequence whenever the selected pll_locked signal is deasserted.
rx_manual[<n> -1:0] Input Asynchronous This optional signal places rx_digitalreset logic controller under automatic or manual control. In manual mode, the rx_digitalreset controller does not respond to the assertion or deassertion of the rx_is_lockedtodata signal. The rx_digitalreset controller asserts rx_ready when the rx_is_lockedtodata signal is asserted.
clock Input N/A A free running system clock input to the Transceiver PHY Reset Controller from which all internal logic is driven. If a free running clock is not available, hold reset until the system clock is stable.
reset Input Asynchronous Asynchronous reset input to the Transceiver PHY Reset Controller. When asserted, all configured reset outputs are asserted. Holding the reset input signal asserted holds all other reset outputs asserted. An option is available to synchronize with the system clock. In synchronous mode, the reset signal needs to stay asserted for at least (2) clock cycles by default.
tx_digitalreset [<n>-1:0] Output Synchronous to the Transceiver PHY Reset Controller input clock. Digital reset for TX channels. The width of this signal depends on the number of TX channels. This signal is asserted when any of the following conditions is true:
  • reset is asserted
  • pll_powerdown is asserted
  • pll_cal_busy is asserted
  • tx_cal_busy is asserted
  • PLL has not reached the initial lock (pll_locked deasserted)
  • pll_locked is deasserted and tx_manual is deasserted
When all of these conditions are false, the reset counter begins its countdown for deassertion of tx_digitalreset.
tx_analogreset [<n>-1:0] Output Synchronous to the Transceiver PHY Reset Controller input clock.

Analog reset for TX channels. The width of this signal depends on the number of TX channels. This signal is asserted when reset is asserted.

This signal follows pll_powerdown, which is deasserted after pll_locked goes high.

tx_ready[<n>-1:0] Output Synchronous to the Transceiver PHY Reset Controller input clock. Status signal to indicate when the TX reset sequence is complete. This signal is deasserted while the TX reset is active. It is asserted a few clock cycles after the deassertion of tx_digitalreset. Some protocol implementations may require you to monitor this signal prior to sending data. The width of this signal depends on the number of TX channels.
rx_digitalreset [<n> -1:0] Output Synchronous to the Transceiver PHY Reset Controller input clock. Digital reset for RX. The width of this signal depends on the number of channels. This signal is asserted when any of the following conditions is true:
  • reset is asserted
  • rx_analogreset is asserted
  • rx_cal_busy is asserted
  • rx_is_lockedtodata is deasserted and rx_manual is deasserted
When all of these conditions are false, the reset counter begins its countdown for deassertion of rx_digitalreset.
rx_analogreset [<n>-1:0] Output Synchronous to the Transceiver PHY Reset Controller input clock.

Analog reset for RX. When asserted, resets the RX CDR and the RX PMA blocks of the transceiver PHY. This signal is asserted when any of the following conditions is true:

  • reset is asserted
  • rx_cal_busy is asserted

The width of this signal depends on the number of channels.

rx_ready[<n>-1:0] Output Synchronous to the Transceiver PHY Reset Controller input clock. Status signal to indicate when the RX reset sequence is complete. This signal is deasserted while the RX reset is active. It is asserted a few clock cycles after the deassertion of rx_digitalreset. Some protocol implementations may require you to monitor this signal prior to sending data. The width of this signal depends on the number of RX channels.
pll_powerdown[<p>-1:0] Output Synchronous to the Transceiver PHY Reset Controller input clock. Asserted to power down a transceiver PLL circuit. When asserted, the selected TX PLL is reset.

Usage Examples for pll_select

  • If a single channel can switch between three TX PLLs, the pll_select signal indicates which one of the selected three TX PLL's pll_locked signal is used to communicate the PLL lock status to the TX reset sequence. In this case, to select the 3-bits wide pll_locked port, the pll_select port is 2-bits wide.
  • If three channels are instantiated with three TX PLLs and with a separate TX reset sequence per channel, the pll_select field is 6-bits wide (2-bits per channel). In this case, pll_select [1:0] represents channel 0, pll_select[3:2] represents channel 1, and pll_select[5:4] represents channel 2. For each channel, a separate pll_locked signal indicates the PLL lock status.
  • If three channels are instantiated with three TX PLLs and with a single TX reset sequence for all three channels, then pll_select field is 2-bits wide. In this case, the same pll_locked signal indicates the PLL lock status for all three channels.
  • If one channel is instantiated with one TX PLL, pll_select field is 1-bit wide. Connect pll_select to logic 0.
  • If three channels are instantiated with only one TX PLL and with a separate TX reset sequence per channel, the pll_select field is 3-bits wide. In this case, pll_select should be set to 0 since there is only one TX PLL available.
Level Two Title