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Ixiasoft
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Ixiasoft
4.2. Transceiver PHY Implementation
Transceiver Reset Endpoints—The Transceiver PHY IP core contains Transceiver Reset Endpoints (TREs)34 .
Transceiver Reset Sequencer—The Quartus Prime software detects the presence of TREs and automatically inserts only one Transceiver Reset Sequencer (TRS)34. The tx_analogreset and rx_analogreset requests from the reset controller (User coded or Transceiver PHY Reset Controller) is received by the TREs. The TRE sends the reset request to the TRS for scheduling. TRS schedules all the requested PMA resets and sends them back to TREs. You can use either Transceiver PHY Reset Controller or your own reset controller. However, for the TRS to work correctly, the required timing duration must be followed. See Figure 147 for required timing duration.
altera_a10_xcvr_clock_module reset_clock (.clk_in(mgmt_clk));
For more information about the CLKUSR pin, refer to the Cyclone® 10 GX Pin Connection Guidelines.