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3.2. Input Reference Clock Sources
The transmitter PLL and the clock data recovery (CDR) block need an input reference clock source to generate the clocks required for transceiver operation. The input reference clock must be stable and free-running at device power-up for proper PLL calibrations.
Cyclone® 10 GX transceiver PLLs have five possible input reference clock sources, depending on jitter requirements:
- Dedicated reference clock pins
- Reference clock network
- The output of another fPLL with PLL cascading
- Receiver input pins
- Global clock or core clock 33
For the best jitter performance, Intel recommends placing the reference clock as close as possible to the transmit PLL. For protocol jitter compliance at a data rate > 10 Gbps, place the reference clock pin in the same triplet as the transmit PLL. The following protocols require the reference clock to be placed in same bank as the transmit PLL:
- OC-192 and 10 GPON
Section Content
Dedicated Reference Clock Pins
Receiver Input Pins
PLL Cascading as an Input Reference Clock Source
Reference Clock Network
Global Clock or Core Clock as an Input Reference Clock