Intel® MAX® 10 Clocking and PLL User Guide

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ID 683047
Date 12/26/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 Clocking and PLL Overview 2. Intel® MAX® 10 Clocking and PLL Architecture and Features 3. Intel® MAX® 10 Clocking and PLL Design Considerations 4. Intel® MAX® 10 Clocking and PLL Implementation Guides 5. ALTCLKCTRL Intel® FPGA IP References 6. Avalon ALTPLL Intel® FPGA IP References 7. Avalon ALTPLL RECONFIG Intel® FPGA IP References 8. Internal Oscillator Intel® FPGA IP References 9. Intel® MAX® 10 Clocking and PLL User Guide Archives 10. Document Revision History for the Intel® MAX® 10 Clocking and PLL User Guide
1. Intel® MAX® 10 Clocking and PLL Overview x
1.1. Clock Networks Overview 1.2. Internal Oscillator Overview 1.3. PLLs Overview
2. Intel® MAX® 10 Clocking and PLL Architecture and Features x
2.1. Clock Networks Architecture and Features 2.2. Internal Oscillator Architecture and Features 2.3. PLLs Architecture and Features
2.1. Clock Networks Architecture and Features x
2.1.1. Global Clock Networks 2.1.2. Clock Pins Introduction 2.1.3. Clock Resources 2.1.4. Global Clock Network Sources 2.1.5. Global Clock Control Block 2.1.6. Global Clock Network Power Down 2.1.7. Clock Enable Signals
2.3. PLLs Architecture and Features x
2.3.1. PLL Architecture 2.3.2. PLL Features 2.3.3. PLL Locations 2.3.4. Clock Pin to PLL Connections 2.3.5. PLL Counter to GCLK Connections 2.3.6. PLL Control Signals 2.3.7. Clock Feedback Modes 2.3.8. PLL External Clock Output 2.3.9. ADC Clock Input from PLL 2.3.10. Spread-Spectrum Clocking 2.3.11. PLL Programmable Parameters 2.3.12. Clock Switchover 2.3.13. PLL Cascading 2.3.14. PLL Reconfiguration
2.3.7. Clock Feedback Modes x
2.3.7.1. Source Synchronous Mode 2.3.7.2. No Compensation Mode 2.3.7.3. Normal Mode 2.3.7.4. Zero-Delay Buffer Mode
2.3.11. PLL Programmable Parameters x
2.3.11.1. Programmable Duty Cycle 2.3.11.2. Programmable Bandwidth 2.3.11.3. Programmable Phase Shift
2.3.12. Clock Switchover x
2.3.12.1. Automatic Clock Switchover 2.3.12.2. Automatic Switchover with Manual Override 2.3.12.3. Manual Clock Switchover
2.3.13. PLL Cascading x
2.3.13.1. PLL-to-PLL Cascading 2.3.13.2. Counter-to-Counter Cascading
3. Intel® MAX® 10 Clocking and PLL Design Considerations x
3.1. Clock Networks Design Considerations 3.2. Internal Oscillator Design Considerations 3.3. PLLs Design Considerations
3.1. Clock Networks Design Considerations x
3.1.1. Guideline: Clock Enable Signals 3.1.2. Guideline: Connectivity Restrictions
3.2. Internal Oscillator Design Considerations x
3.2.1. Guideline: Connectivity Restrictions
3.3. PLLs Design Considerations x
3.3.1. Guideline: PLL Control Signals 3.3.2. Guideline: Connectivity Restrictions 3.3.3. Guideline: Self-Reset 3.3.4. Guideline: Output Clocks 3.3.5. Guideline: PLL Cascading 3.3.6. Guideline: Clock Switchover 3.3.7. Guideline: .mif Streaming in PLL Reconfiguration 3.3.8. Guideline: scandone Signal for PLL Reconfiguration
4. Intel® MAX® 10 Clocking and PLL Implementation Guides x
4.1. ALTCLKCTRL Intel® FPGA IP 4.2. Avalon ALTPLL Intel® FPGA IP 4.3. Avalon ALTPLL RECONFIG Intel® FPGA IP 4.4. Internal Oscillator Intel® FPGA IP
4.2. Avalon ALTPLL Intel® FPGA IP x
4.2.1. Expanding the PLL Lock Range 4.2.2. Programmable Bandwidth with Advanced Parameters 4.2.3. PLL Dynamic Reconfiguration Implementation 4.2.4. Dynamic Phase Configuration Implementation
4.2.3. PLL Dynamic Reconfiguration Implementation x
4.2.3.1. Post-Scale Counters (C0 to C4) 4.2.3.2. Scan Chain 4.2.3.3. Charge Pump and Loop Filter 4.2.3.4. Bypassing PLL Counter
4.2.4. Dynamic Phase Configuration Implementation x
4.2.4.1. Dynamic Phase Configuration Counter Selection 4.2.4.2. Dynamic Phase Configuration with Advanced Parameters
4.3. Avalon ALTPLL RECONFIG Intel® FPGA IP x
4.3.1. Obtaining the Resource Utilization Report
5. ALTCLKCTRL Intel® FPGA IP References x
5.1. ALTCLKCTRL Intel® FPGA IP Parameters 5.2. ALTCLKCTRL Intel® FPGA IP Ports and Signals
6. Avalon ALTPLL Intel® FPGA IP References x
6.1. Avalon ALTPLL Intel® FPGA IP Parameters 6.2. Avalon ALTPLL Intel® FPGA IP Ports and Signals
6.1. Avalon ALTPLL Intel® FPGA IP Parameters x
6.1.1. Operation Modes Parameter Settings 6.1.2. PLL Control Signals Parameter Settings 6.1.3. Programmable Bandwidth Parameter Settings 6.1.4. Clock Switchover Parameter Settings 6.1.5. PLL Dynamic Reconfiguration Parameter Settings 6.1.6. Dynamic Phase Configuration Parameter Settings 6.1.7. Output Clocks Parameter Settings
7. Avalon ALTPLL RECONFIG Intel® FPGA IP References x
7.1. Avalon ALTPLL RECONFIG Intel® FPGA IP Parameters 7.2. Avalon ALTPLL RECONFIG Intel® FPGA IP Ports and Signals 7.3. Avalon ALTPLL RECONFIG Intel® FPGA IP Counter Settings
8. Internal Oscillator Intel® FPGA IP References x
8.1. Internal Oscillator Intel® FPGA IP Parameters 8.2. Internal Oscillator Intel® FPGA IP Ports and Signals
1. Intel® MAX® 10 Clocking and PLL Overview
2. Intel® MAX® 10 Clocking and PLL Architecture and Features
3. Intel® MAX® 10 Clocking and PLL Design Considerations
4. Intel® MAX® 10 Clocking and PLL Implementation Guides
5. ALTCLKCTRL Intel® FPGA IP References
6. Avalon ALTPLL Intel® FPGA IP References
7. Avalon ALTPLL RECONFIG Intel® FPGA IP References
8. Internal Oscillator Intel® FPGA IP References
9. Intel® MAX® 10 Clocking and PLL User Guide Archives
10. Document Revision History for the Intel® MAX® 10 Clocking and PLL User Guide

7.2. Avalon ALTPLL RECONFIG Intel® FPGA IP Ports and Signals

Table 25.   Avalon ALTPLL RECONFIG Input Ports for Intel® MAX® 10 Devices
Port Name Condition Description
clock

Required

Clock input for loading individual parameters. This signal also clocks the PLL during reconfiguration.

The clock input port must be connected to a valid clock.

Refer to the Intel® MAX® 10 FPGA Device Datasheet for the clock fMAX.

reset

Required

Asynchronous reset input to the IP.

Intel recommends that you reset this IP before first use to guarantee that it is in a valid state. However, it does power up in the reset state. This port must be connected.

data_in[]

Optional

Data input that provides parameter value when writing parameters.

This 9-bit input port provides the data to be written to the scan cache during a write operation. The bit width of the counter parameter to be written determines the number of bits of data_in[] that are read into the cache.

For example, the low bit count of the C0 counter is 8-bit wide, so data_in[7..0] is read to the correct cache location. The bypass mode for the C0 counter is 1-bit wide, so data_in[0] is read for the value of this parameter.

If omitted, the default value is 0.
counter_type[]

Optional

Specifies the counter type.

An input port in the form of a 4-bit bus that selects which counter type should be selected for the corresponding operation (read, write, or reconfig).

Refer to the counter_type[3..0] settings table for the mapping between the counter_type value and the physical counter to be set.

counter_param[]

Optional

Specifies the parameter for the value specified in the counter_type port.

An input port in the form of a 3-bit bus that selects which parameter for the given counter type should be updated. The mapping to each parameter type and the corresponding parameter bit-width are defined in the counter_param[3..0] settings table.

read_param

Optional

Reads the parameter specified with the counter_type and counter_param ports from cache and fed to the data_out[] port.

When asserted, the read_param signal indicates that the scan cache should be read and fed to data_out[]. The bit location of the scan cache and the number of bits read and sent to data_out[] depend on the counter_type and counter_param values. The read_param signal is sampled at the rising clock edge. If the read_param signal is asserted, the parameter value is read from the cache. Assert the read_param signal for 1 clock cycle only to prevent the parameter from being read twice.

The busy signal is asserted on the rising clock edge following the assertion of the read_param signal. While the parameter is read, the busy signal remains asserted. After the busy signal is deasserted, the value on data_out[] is valid and the next parameter can be loaded. While the busy signal is asserted, the value on data_out[] is not valid.

When the read_param signal is asserted, the busy signal is only asserted on the following rising edge of the clock and not on the same clock cycle as the read_param signal.

write_param

Optional

Writes the parameter specified with the counter_type and counter_param ports to the cache with the value specified on the data_in[] port.

When asserted, the write_param signal indicates that the value on data_in[] should be written to the parameter specified by counter_type[] and counter_param[]. The number of bits read from the data_in[] port depends on the parameter. The write_param signal is sampled at the rising clock edge. If the write_param signal is asserted, the parameter value is written to the cache. Assert the write_param signal for 1 clock cycle only to prevent the parameter from being written twice.

The busy signal is asserted on the rising clock edge following the assertion of the write_param signal. While the parameter is being written, the busy signal remains asserted and input to data_in[] is ignored. After the busy signal is deasserted, the next parameter can be written.

When the write_param signal is asserted, the busy signal is only asserted on the following rising edge of the clock. The busy signal is not asserted on the same clock cycle as the write_param signal.

reconfig

Required

Specifies that the PLL should be reconfigured with the PLL settings specified in the current cache.

When asserted, the reconfig signal indicates that the PLL should be reconfigured with the values in the cache. The reconfig signal is sampled at the rising clock edge. If the reconfig signal is asserted, the cached settings are loaded in the PLL. Assert the reconfig signal for 1 clock cycle only to prevent reloading the PLL configuration. The busy signal is asserted on the rising clock edge following the assertion of the reconfig signal. While the PLL is being loaded, the busy signal remains asserted. After the busy signal is deasserted, the parameter values can be modified again.

During and after reconfiguration, the scan chain data cache remains unchanged. This allows you to easily create a new set of reconfiguration settings using only one parameter.

If write_param has not been asserted since the previous assertion of reconfig, the entire scan chain is shifted in to the PLL again.

When the reconfig signal is asserted, the busy signal is only asserted on the following rising edge of the clock. The busy signal is not asserted on the same clock cycle as the reconfig signal.

pll_areset_in

Optional

Input signal indicating that the PLL should be reset.

When asserted, the pll_areset_in signal indicates the PLL IP should be reset. This port defaults to 0 if left unconnected. When using the Avalon ALTPLL RECONFIG Intel® FPGA IP in a design, you cannot reset the PLL in any other way. You must use this IP port to manually reset the PLL.

pll_scandone

Optional

Input port for the Avalon® Avalon ALTPLL RECONFIG Intel® FPGA IP. This port is driven by the PLL's scandone output signal and determines when the PLL is reconfigured.

pll_scandataout

Required

Input port driven by the scandataout signal from the Avalon ALTPLL Intel® FPGA IP. Use this port to read the current configuration of the Avalon ALTPLL Intel® FPGA IP. This input port holds the Avalon ALTPLL scan data output from the dynamically reconfigurable bits. The pll_scandataout port must be connected to the scandataout port of the PLL. The activity on this port can only be observed when the reconfig signal is asserted.

Table 26.   Avalon ALTPLL RECONFIG Output Ports for Intel® MAX® 10 Devices
Port Name Condition Description
data_out[]

Optional

Data read from the cache when read_param is asserted.

This 9-bit output bus provides the parameter data to the user. When the read_param signal is asserted, the values on counter_type[] and counter_param[] determine the parameter value that is loaded from cache and driven on the data_out[] bus. When the IP deasserts the busy signal, the appropriate bits of the bus (for example,[0] or [3..0]) hold a valid value.

busy

Optional

Indicates that the PLL is reading or writing a parameter to the cache, or is configuring the PLL.

While the busy signal is asserted, no parameters can be read or written, and no reconfiguration can be initiated. Changes to the IP can be made only when the busy signal is not asserted. The signal goes high when the read_param, write_param, or reconfig input port is asserted, and remains high until the specified operation is complete. In the case of a reconfiguration operation, the busy signal remains high until the pll_areset signal is asserted and then deasserted.

pll_areset

Required

Drives the areset port on the PLL to be reconfigured.

The pll_areset port must be connected to the areset port of the Avalon ALTPLL Intel® FPGA IP for the reconfiguration to function correctly. This signal is active high. The pll_areset is asserted when pll_areset_in is asserted, or, after reconfiguration, at the next rising clock edge after the scandone signal goes high. If you use the Avalon ALTPLL RECONFIG Intel® FPGA IP, use the pll_areset output port to drive the PLL areset port.

pll_configupdate

Optional

Drives the configupdate port on the PLL to be reconfigured. When asserted, the pll_configupdate port loads selected data to PLL configuration latches. The signal is asserted after the final data bit is sent out.

pll_scanclk

Required

Drives the scanclk port on the PLL to be reconfigured. For information about the maximum scanclk frequency for the various devices, refer to the respective device handbook.

pll_scanclkena

Optional

This port acts as a clock enable for the scanclk port on the PLL to be reconfigured.

Reconfiguration begins on the first rising edge of pll_scanclk after pll_scanclkena assertion. On the first falling edge of pll_scanclk, after the deassertion of the pll_scanclkena signal, the IP stops scanning data to the PLL.

pll_scandata

Required

Drives the scandata port on the PLL to be reconfigured.

This output port from the IP holds the scan data input to the PLL for the dynamically reconfigurable bits. The pll_scandata port sends scandata to the PLL. Any activity on this port can only be observed when the reconfig signal is asserted.

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