Intel® MAX® 10 Clocking and PLL User Guide

ID 683047
Date 12/26/2023
Public
Document Table of Contents

6.1.5. PLL Dynamic Reconfiguration Parameter Settings

The parameter settings for the normal dynamic reconfiguration scheme are located on the PLL Reconfiguration page of the Avalon ALTPLL Intel® FPGA IP parameter editor.

Table 19.  PLL Dynamic Reconfiguration Parameter Editor Settings
Parameter Value Description
Create optional inputs for dynamic reconfiguration On or Off Turn on this option to enable all the PLL reconfiguration ports for this instantiation—scanclk, scanclkena, scandata, scandone, scandataout, and configupdate.
Initial Configuration File Specify the location of the configuration file that is used to initialize the Avalon ALTPLL RECONFIG Intel® FPGA IP.
Additional Configuration File(s) Specify additional configuration file. This file might contain additional settings for the PLL, or might be used to initialize the Avalon ALTPLL RECONFIG Intel® FPGA IP.