P-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 683038
Date 3/28/2022
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Document Table of Contents
Document Table of Contents x
1. About the P-tile Avalon® Streaming Intel® FPGA IP for PCI Express Design Examples 2. Quick Start Guide 3. P-tile Avalon® Streaming IP for PCI Express* Design Example User Guide Archives 4. Document Revision History for the Intel® P-Tile Avalon® Streaming Hard IP for PCIe* Design Example User Guide
1. About the P-tile Avalon® Streaming Intel® FPGA IP for PCI Express Design Examples x
1.1. Overview 1.2. Functional Description for the Programmed Input/Output (PIO) Design Example 1.3. Functional Description for the Single Root I/O Virtualization (SR-IOV) Design Example 1.4. Functional Description for the Performance Design Example 1.5. Hardware and Software Requirements
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Compiling the Design Example 2.5. Installing the Linux Kernel Driver 2.6. Running the Design Example
2.3. Simulating the Design Example x
2.3.1. Testbench
2.3.1. Testbench x
2.3.1.1. Test Driver Module 2.3.1.2. PIO Design Example Testbench 2.3.1.3. SR-IOV Design Example Testbench 2.3.1.4. Performance Design Example Testbench
2.6. Running the Design Example x
2.6.1. Running the PIO Design Example 2.6.2. Running the SR-IOV Design Example 2.6.3. Running the Performance Design Example
1. About the P-tile Avalon® Streaming Intel® FPGA IP for PCI Express Design Examples
2. Quick Start Guide
3. P-tile Avalon® Streaming IP for PCI Express* Design Example User Guide Archives
4. Document Revision History for the Intel® P-Tile Avalon® Streaming Hard IP for PCIe* Design Example User Guide

1.1. Overview

The following table presents an overview of the design examples supported by the P-tile Avalon® Streaming IP for PCI Express:
Table 1.  Design Examples Overview
Design Example Hard IP Mode Simulation Hardware
PIO Gen4 x16 512-bit (350 MHz or above) Endpoint Supports Siemens EDA QuestaSim*, VCS* and Riviera-Pro* simulators. Supported for Intel® Stratix® 10 DX P-Tile ES1/ Production FPGA Development Kit and Intel® Agilex™ F-Series P-Tile ES0 FPGA Development Kit.
Gen3 x16 512-bit Endpoint
Gen4 x8x8 256-bit (350 MHz or above) Endpoint
Gen3 x8x8 256-bit Endpoint
SR-IOV Gen4 x16 512-bit (350 MHz or above) Endpoint Supports Siemens EDA QuestaSim*, VCS* and Riviera-Pro* simulators. Supported for Intel® Stratix® 10 DX P-Tile ES1/ Production FPGA Development Kit and Intel® Agilex™ F-Series P-Tile ES0 FPGA Development Kit.
Gen3 x16 512-bit Endpoint
Gen4 x8x8 256-bit (350 MHz or above) Endpoint
Gen3 x8x8 256-bit Endpoint
Performance Gen4 x16 512-bit (500 MHz) Endpoint Supports VCS* simulator only. Supported for Intel® Stratix® 10 DX P-Tile ES1/ Production FPGA Development Kit and Intel® Agilex™ F-Series P-Tile ES0 FPGA Development Kit. (*)
Note: (*) Supported in Intel® Quartus® Prime releases from 22.1 onward. For release 21.4, an Intel® Quartus® Prime patch is required. Refer to the Intel KDB for details.
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