F-Tile Ethernet Intel® FPGA Hard IP User Guide

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ID 683023
Date 11/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. F-Tile Ethernet Intel® FPGA Hard IP Parameters 4. Functional Description 5. Clocks 6. Resets 7. Interface Overview 8. Configuration Registers 9. Supported Modules and IPs 10. Supported Tools 11. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives 12. Document Revision History for the F-Tile Ethernet Intel® FPGA Hard IP User Guide
1. Overview x
1.1. Ethernet System in F-Tile Overview 1.2. F-Tile Ethernet Intel® FPGA Hard IP Overview
1.2. F-Tile Ethernet Intel® FPGA Hard IP Overview x
1.2.1. Device Family Support 1.2.2. Device Speed Grade Support 1.2.3. Resource Utilization 1.2.4. Round-trip Latency 1.2.5. Release Information
2. Getting Started x
2.1. Installing and Licensing F-Tile Ethernet Intel® FPGA Hard IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Reference and System PLL Clock for your IP Design 2.4. Generated File Structure 2.5. Generating Tile Files 2.6. IP Core Testbenches
2.4. Generated File Structure x
2.4.1. Generating IP-XACT File
4. Functional Description x
4.1. Datapath Description 4.2. F-Tile Ethernet Intel® FPGA Hard IP MAC 4.3. PCS, OTN, and FlexE Modes 4.4. Precision Time Protocol 4.5. Auto-Negotiation and Link Training
4.2. F-Tile Ethernet Intel® FPGA Hard IP MAC x
4.2.1. MAC TX Datapath 4.2.2. MAC RX Datapath 4.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) 4.2.4. Link Fault Signaling 4.2.5. Order of Ethernet Transmission
4.2.1. MAC TX Datapath x
4.2.1.1. TX Preamble, Start, and SFD Insertion 4.2.1.2. Source Address Insertion 4.2.1.3. Length/Type Field Processing 4.2.1.4. Frame Padding 4.2.1.5. Frame Check Sequence (CRC-32) Insertion 4.2.1.6. Inter-Packet Gap Generation and Insertion 4.2.1.7. TX Packing Logic
4.2.2. MAC RX Datapath x
4.2.2.1. RX Preamble Processing 4.2.2.2. RX Strict SFD Checking 4.2.2.3. RX FCS Checking 4.2.2.4. RX Malformed Packet Handling 4.2.2.5. Removing PAD Bytes and FCS Bytes from RX Frames 4.2.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors 4.2.2.7. Inter-Packet Gap
4.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
4.2.3.1. Conditions Triggering XOFF Frame Transmission 4.2.3.2. Conditions Triggering XON Frame Transmission 4.2.3.3. Pause Control and Generation Interface 4.2.3.4. Pause Control Frame Filtering
4.3. PCS, OTN, and FlexE Modes x
4.3.1. PCS Mode 4.3.2. OTN Mode 4.3.3. FlexE Mode
4.4. Precision Time Protocol x
4.4.1. Features 4.4.2. PTP Timestamp Accuracy 4.4.3. PTP Client Flow 4.4.4. RX Virtual Lane Offset Calculation for No FEC Variants 4.4.5. Virtual Lane Order and Offset Values 4.4.6. UI Adjustment 4.4.7. Reference Time Interval 4.4.8. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware) 4.4.9. UI Value and PMA Delay 4.4.10. Routing Delay Adjustment for Advanced Timestamp Accuracy Mode 4.4.11. Routing Delay Adjustment for Basic Timestamp Accuracy Mode
4.4.3. PTP Client Flow x
4.4.3.1. PTP TX Client Flow 4.4.3.2. PTP RX Client Flow
4.4.6. UI Adjustment x
4.4.6.1. TX UI Adjustment 4.4.6.2. RX UI Adjustment
5. Clocks x
5.1. Clock Connections in Single Instance Operation 5.2. Clock Connections in Multiple Instance Operation 5.3. Clock Connections in MAC Asynchronous FIFO Operation 5.4. Clock Connections in PTP-Based Synchronous and Asynchronous Operation 5.5. Clock Connections in Synchronous Ethernet Operation 5.6. Custom Cadence
6. Resets x
6.1. Reset Signals 6.2. Reset Sequence
7. Interface Overview x
7.1. Status Interface 7.2. TX MAC Avalon ST Client Interface 7.3. RX MAC Avalon ST Aligned Client Interface 7.4. TX MAC Segmented Client Interface 7.5. RX MAC Segmented Client Interface 7.6. MAC Flow Control Interface 7.7. PCS Mode TX Interface 7.8. PCS Mode RX Interface 7.9. FlexE and OTN Mode TX Interface 7.10. FlexE and OTN Mode RX Interface 7.11. Custom Rate Interface 7.12. 32-bit Soft CWBIN Counters 7.13. Reconfiguration Interfaces 7.14. Precision Time Protocol Interface
7.2. TX MAC Avalon ST Client Interface x
7.2.1. TX MAC Avalon ST Client Interface with Disabled Preamble Passthrough 7.2.2. TX MAC Avalon ST Client Interface with Enabled Preamble Passthrough 7.2.3. Using MAC Avalon ST skip_crc Signal to Control Source Address, PAD, and CRC Insertion 7.2.4. Using MAC Avalon ST i_tx_error Signal to Mark Packets Invalid
7.3. RX MAC Avalon ST Aligned Client Interface x
7.3.1. RX MAC Avalon ST Client Interface with Disabled Preamble Passthrough 7.3.2. RX MAC Avalon ST Client Interface with Enabled Passthrough and RX CRC Forwarding 7.3.3. RX MAC Adapter Limitations 7.3.4. RX MAC Avalon ST Client Interface Status
7.4. TX MAC Segmented Client Interface x
7.4.1. TX MAC Segmented Client Interface with Disabled Preamble Passthrough 7.4.2. TX MAC Segmented Client Interface with Enabled Preamble Passthrough 7.4.3. Using MAC Segmented skip_crc Signal to Control Source Address, PAD, and CRC Insertion 7.4.4. Using MAC Segmented i_tx_mac_error to Mark Packets Invalid
7.5. RX MAC Segmented Client Interface x
7.5.1. RX MAC Segmented Client Interface with Disabled Preamble Passthrough 7.5.2. RX MAC Segmented Client Interface with Enabled Passthrough and RX CRC Forwarding 7.5.3. RX MAC Segmented Client Interface Status and Errors
7.13. Reconfiguration Interfaces x
7.13.1. Ethernet Reconfiguration Interfaces 7.13.2. Transceiver Reconfiguration Interfaces
7.14. Precision Time Protocol Interface x
7.14.1. Time-of-Day Interface 7.14.2. TX 2-Step Timestamp Interface 7.14.3. TX 1-Step Timestamp Interface 7.14.4. RX Timestamp Interface 7.14.5. PTP Status Interface 7.14.6. PTP Tile Interface
7.14.3. TX 1-Step Timestamp Interface x
7.14.3.1. PTP Field Offset for 1-Step Operation
8. Configuration Registers x
8.1. Ethernet Avalon® Memory-Mapped Interface Address Space 8.2. Transceiver Avalon® Memory-Mapped Interface Address Space
8.1. Ethernet Avalon® Memory-Mapped Interface Address Space x
8.1.1. Ethernet Hard IP Core CSRs 8.1.2. FEC and Transceiver Control and Status Registers
9. Supported Modules and IPs x
9.1. F-Tile Auto-Negotiation and Link Training For Ethernet Intel® FPGA IP 9.2. PTP Tile Adapter
9.1. F-Tile Auto-Negotiation and Link Training For Ethernet Intel® FPGA IP x
9.1.1. Overview 9.1.2. Release Information 9.1.3. Functional Description 9.1.4. Parameters 9.1.5. Clocks and Resets 9.1.6. Registers
9.2. PTP Tile Adapter x
9.2.1. Overview 9.2.2. Clocks, Reset, and Interface Ports 9.2.3. PTP Asymmetry Delay Reconfiguration Interface 9.2.4. PTP Peer-to-Peer MeanPathDelay Reconfiguration Interface
10. Supported Tools x
10.1. F-Tile Channel Placement Tool 10.2. Ethernet Toolkit Overview
10.2. Ethernet Toolkit Overview x
10.2.1. Features
1. Overview
2. Getting Started
3. F-Tile Ethernet Intel® FPGA Hard IP Parameters
4. Functional Description
5. Clocks
6. Resets
7. Interface Overview
8. Configuration Registers
9. Supported Modules and IPs
10. Supported Tools
11. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives
12. Document Revision History for the F-Tile Ethernet Intel® FPGA Hard IP User Guide

7.4. TX MAC Segmented Client Interface

The F-Tile Ethernet Intel® FPGA Hard IP TX MAC segmented client interface allows you to write frame data to the TX MAC for transmission. The packets may start on any 8-byte segment.
Attention: To achieve the maximum throughput when using the TX MAC segmented interface, the input packets need to be packed tightly, leaving no idle segments in between.
Table 42.  Signals of the TX MAC Segmented Client InterfaceAll interface signals are clocked by the TX clock.

Signal Name

Width

Description

i_tx_mac_data[1023:0]

i_tx_mac_data[511:0]

i_tx_mac_data[255:0]

i_tx_mac_data[127:0]

i_tx_mac_data[63:0]

1024 bits (400GE)

512 bits (200GE)

256 bits (100GE)

128 bits (50GE/40GE)

64 bits (25GE/10GE)

 Input data to the MAC when the rate is 10GE/25/40GE/50GE/100GE/200GE/400GE. Bit 0 is the LSB.
i_tx_mac_valid 1 bit

When asserted, the TX data signal is valid on this cycle. Must follow at a fixed latency relative to o_tx_mac_ready, and may go low during transmission of a packet.

When deasserted, values of input signals on the interface are hold constant.

i_tx_mac_inframe[15:0]

i_tx_mac_inframe[7:0]

i_tx_mac_inframe[3:0]

i_tx_mac_inframe[1:0]

i_tx_mac_inframe[0]

16 bits (400GE)

8 bits (200GE)

4 bits (100GE)

2 bits (50GE/40GE)

1 bits (25GE/10GE)

Indicates valid data in each segment for specific rate.

Along with the previous segment's inframe signal, this signal indicates the SOP and EOP location.

i_tx_mac_eop_empty[47:0]

i_tx_mac_eop_empty[23:0]

i_tx_mac_eop_empty[11:0]

i_tx_mac_eop_empty[5:0]

i_tx_mac_eop_empty[2:0]

48 bits (400GE)

24 bits (200GE)

12 bits (100GE)

6 bits (50GE/40GE)

3 bits (25GE/10GE)

The empty signal indicates the number of empty bytes in that segment at the end of the MAC frame.

o_tx_mac_ready

1 bit

The ready signal indicates the MAC is ready to receive data in normal operational mode.

i_tx_mac_error[15:0]

i_tx_mac_error[7:0]

i_tx_mac_error[3:0]

i_tx_mac_error[1:0]

i_tx_mac_error[0]

16 bits (400GE)

8 bits (200GE)

4 bits (100GE)

2 bits (50GE/40GE)

1 bits (25GE/10GE)

The error signal cause the TX frame treated as an error. Must assert in the segment where the frame ends.

i_tx_mac_skip_crc[15:0]

i_tx_mac_skip_crc[7:0]

i_tx_mac_skip_crc[3:0]

i_tx_mac_skip_crc[1:0]

i_tx_mac_skip_crc[0]

16 bits (400GE)

8 bits (200GE)

4 bits (100GE)

2 bits (50GE/40GE)

1 bits (25GE/10GE)

The skip CRC signal instructs the MAC to not insert CRC/PAD in a current packet. Must be asserted along with all valid data segments for the packet.

Figure 41. Transmitting Data Using the TX MAC Segmented Client Interface

The figure above shows how to transmit data using the TX MAC segmented client interface. In this example, the figure shows a 100GE port transmitting several packets, represented by 4 segments.

  • Packets may start on any 8-byte segment of i_tx_mac_data (Segmented). The i_tx_mac_inframe transition from 0 to 1 (between two consecutive segments) indicates a start of packet (SOP). The SOP begins at a segment where i_tx_mac_frame is set to 1.
  • For multisegmented interfaces, a new packet may start and the previous packet end are within the same cycle.
  • The byte order for the TX MAC segmented client interface is the reverse of the MAC Avalon ST client byte order. The bytes flow from right to left, LSB to MSB. The first transmitted byte from the interface is the i_tx_mac_data[7:0].
  • The bit order for the TX MAC segmented client interface is the same as the MAC Avalon ST client bit order. The first transmitted bit from the interface is the i_tx_mac_data[0].
    • The i_tx_mac_valid signal asserts only when the o_tx_mac_ready signal is asserted. The i_tx_mac_valid signal deasserts when the o_tx_mac_ready signal is deasserted.
    • The i_tx_mac_valid and the o_tx_mac_ready signals can be spaced by a fixed latency between 1 to 7 clock cycles.
    • When i_tx_mac_valid deasserts, i_tx_mac_data, i_tx_mac_inframe, i_tx_mac_eop_empty, i_tx_mac_error. and i_tx_skip_crc signals must be paused for as many cycles as o_tx_mac_ready is deasserted.
  • When the frame ends, i_tx_mac_eop_empty is set to the number of unused bytes in i_tx_mac_data.
    • The i_tx_mac_eop_empty transition from 1 to 0 (between two consecutive segments) indicates the end of packet (EOP). The EOP ends in the segment where i_tx_mac_inframe is set to 0.
    • The minimum number of bytes on the last cycle is 1.

Section Content
TX MAC Segmented Client Interface with Disabled Preamble Passthrough
TX MAC Segmented Client Interface with Enabled Preamble Passthrough
Using MAC Segmented skip_crc Signal to Control Source Address, PAD, and CRC Insertion
Using MAC Segmented i_tx_mac_error to Mark Packets Invalid

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