F-Tile Ethernet Intel® FPGA Hard IP User Guide

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ID 683023
Date 11/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. F-Tile Ethernet Intel® FPGA Hard IP Parameters 4. Functional Description 5. Clocks 6. Resets 7. Interface Overview 8. Configuration Registers 9. Supported Modules and IPs 10. Supported Tools 11. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives 12. Document Revision History for the F-Tile Ethernet Intel® FPGA Hard IP User Guide
1. Overview x
1.1. Ethernet System in F-Tile Overview 1.2. F-Tile Ethernet Intel® FPGA Hard IP Overview
1.2. F-Tile Ethernet Intel® FPGA Hard IP Overview x
1.2.1. Device Family Support 1.2.2. Device Speed Grade Support 1.2.3. Resource Utilization 1.2.4. Round-trip Latency 1.2.5. Release Information
2. Getting Started x
2.1. Installing and Licensing F-Tile Ethernet Intel® FPGA Hard IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Reference and System PLL Clock for your IP Design 2.4. Generated File Structure 2.5. Generating Tile Files 2.6. IP Core Testbenches
2.4. Generated File Structure x
2.4.1. Generating IP-XACT File
4. Functional Description x
4.1. Datapath Description 4.2. F-Tile Ethernet Intel® FPGA Hard IP MAC 4.3. PCS, OTN, and FlexE Modes 4.4. Precision Time Protocol 4.5. Auto-Negotiation and Link Training
4.2. F-Tile Ethernet Intel® FPGA Hard IP MAC x
4.2.1. MAC TX Datapath 4.2.2. MAC RX Datapath 4.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) 4.2.4. Link Fault Signaling 4.2.5. Order of Ethernet Transmission
4.2.1. MAC TX Datapath x
4.2.1.1. TX Preamble, Start, and SFD Insertion 4.2.1.2. Source Address Insertion 4.2.1.3. Length/Type Field Processing 4.2.1.4. Frame Padding 4.2.1.5. Frame Check Sequence (CRC-32) Insertion 4.2.1.6. Inter-Packet Gap Generation and Insertion 4.2.1.7. TX Packing Logic
4.2.2. MAC RX Datapath x
4.2.2.1. RX Preamble Processing 4.2.2.2. RX Strict SFD Checking 4.2.2.3. RX FCS Checking 4.2.2.4. RX Malformed Packet Handling 4.2.2.5. Removing PAD Bytes and FCS Bytes from RX Frames 4.2.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors 4.2.2.7. Inter-Packet Gap
4.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
4.2.3.1. Conditions Triggering XOFF Frame Transmission 4.2.3.2. Conditions Triggering XON Frame Transmission 4.2.3.3. Pause Control and Generation Interface 4.2.3.4. Pause Control Frame Filtering
4.3. PCS, OTN, and FlexE Modes x
4.3.1. PCS Mode 4.3.2. OTN Mode 4.3.3. FlexE Mode
4.4. Precision Time Protocol x
4.4.1. Features 4.4.2. PTP Timestamp Accuracy 4.4.3. PTP Client Flow 4.4.4. RX Virtual Lane Offset Calculation for No FEC Variants 4.4.5. Virtual Lane Order and Offset Values 4.4.6. UI Adjustment 4.4.7. Reference Time Interval 4.4.8. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware) 4.4.9. UI Value and PMA Delay 4.4.10. Routing Delay Adjustment for Advanced Timestamp Accuracy Mode 4.4.11. Routing Delay Adjustment for Basic Timestamp Accuracy Mode
4.4.3. PTP Client Flow x
4.4.3.1. PTP TX Client Flow 4.4.3.2. PTP RX Client Flow
4.4.6. UI Adjustment x
4.4.6.1. TX UI Adjustment 4.4.6.2. RX UI Adjustment
5. Clocks x
5.1. Clock Connections in Single Instance Operation 5.2. Clock Connections in Multiple Instance Operation 5.3. Clock Connections in MAC Asynchronous FIFO Operation 5.4. Clock Connections in PTP-Based Synchronous and Asynchronous Operation 5.5. Clock Connections in Synchronous Ethernet Operation 5.6. Custom Cadence
6. Resets x
6.1. Reset Signals 6.2. Reset Sequence
7. Interface Overview x
7.1. Status Interface 7.2. TX MAC Avalon ST Client Interface 7.3. RX MAC Avalon ST Aligned Client Interface 7.4. TX MAC Segmented Client Interface 7.5. RX MAC Segmented Client Interface 7.6. MAC Flow Control Interface 7.7. PCS Mode TX Interface 7.8. PCS Mode RX Interface 7.9. FlexE and OTN Mode TX Interface 7.10. FlexE and OTN Mode RX Interface 7.11. Custom Rate Interface 7.12. 32-bit Soft CWBIN Counters 7.13. Reconfiguration Interfaces 7.14. Precision Time Protocol Interface
7.2. TX MAC Avalon ST Client Interface x
7.2.1. TX MAC Avalon ST Client Interface with Disabled Preamble Passthrough 7.2.2. TX MAC Avalon ST Client Interface with Enabled Preamble Passthrough 7.2.3. Using MAC Avalon ST skip_crc Signal to Control Source Address, PAD, and CRC Insertion 7.2.4. Using MAC Avalon ST i_tx_error Signal to Mark Packets Invalid
7.3. RX MAC Avalon ST Aligned Client Interface x
7.3.1. RX MAC Avalon ST Client Interface with Disabled Preamble Passthrough 7.3.2. RX MAC Avalon ST Client Interface with Enabled Passthrough and RX CRC Forwarding 7.3.3. RX MAC Adapter Limitations 7.3.4. RX MAC Avalon ST Client Interface Status
7.4. TX MAC Segmented Client Interface x
7.4.1. TX MAC Segmented Client Interface with Disabled Preamble Passthrough 7.4.2. TX MAC Segmented Client Interface with Enabled Preamble Passthrough 7.4.3. Using MAC Segmented skip_crc Signal to Control Source Address, PAD, and CRC Insertion 7.4.4. Using MAC Segmented i_tx_mac_error to Mark Packets Invalid
7.5. RX MAC Segmented Client Interface x
7.5.1. RX MAC Segmented Client Interface with Disabled Preamble Passthrough 7.5.2. RX MAC Segmented Client Interface with Enabled Passthrough and RX CRC Forwarding 7.5.3. RX MAC Segmented Client Interface Status and Errors
7.13. Reconfiguration Interfaces x
7.13.1. Ethernet Reconfiguration Interfaces 7.13.2. Transceiver Reconfiguration Interfaces
7.14. Precision Time Protocol Interface x
7.14.1. Time-of-Day Interface 7.14.2. TX 2-Step Timestamp Interface 7.14.3. TX 1-Step Timestamp Interface 7.14.4. RX Timestamp Interface 7.14.5. PTP Status Interface 7.14.6. PTP Tile Interface
7.14.3. TX 1-Step Timestamp Interface x
7.14.3.1. PTP Field Offset for 1-Step Operation
8. Configuration Registers x
8.1. Ethernet Avalon® Memory-Mapped Interface Address Space 8.2. Transceiver Avalon® Memory-Mapped Interface Address Space
8.1. Ethernet Avalon® Memory-Mapped Interface Address Space x
8.1.1. Ethernet Hard IP Core CSRs 8.1.2. FEC and Transceiver Control and Status Registers
9. Supported Modules and IPs x
9.1. F-Tile Auto-Negotiation and Link Training For Ethernet Intel® FPGA IP 9.2. PTP Tile Adapter
9.1. F-Tile Auto-Negotiation and Link Training For Ethernet Intel® FPGA IP x
9.1.1. Overview 9.1.2. Release Information 9.1.3. Functional Description 9.1.4. Parameters 9.1.5. Clocks and Resets 9.1.6. Registers
9.2. PTP Tile Adapter x
9.2.1. Overview 9.2.2. Clocks, Reset, and Interface Ports 9.2.3. PTP Asymmetry Delay Reconfiguration Interface 9.2.4. PTP Peer-to-Peer MeanPathDelay Reconfiguration Interface
10. Supported Tools x
10.1. F-Tile Channel Placement Tool 10.2. Ethernet Toolkit Overview
10.2. Ethernet Toolkit Overview x
10.2.1. Features
1. Overview
2. Getting Started
3. F-Tile Ethernet Intel® FPGA Hard IP Parameters
4. Functional Description
5. Clocks
6. Resets
7. Interface Overview
8. Configuration Registers
9. Supported Modules and IPs
10. Supported Tools
11. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives
12. Document Revision History for the F-Tile Ethernet Intel® FPGA Hard IP User Guide

4.4.4. RX Virtual Lane Offset Calculation for No FEC Variants

  1. Lock the RX PCS.

    The RX PCS must be fully aligned before extracting VL Offset data. Wait for o_rx_pcs_fully_aligned to be asserted.

  2. Read the VL data for each of the Local Virtual Lanes (VL):

    Perform the read operation from o_rx_pcs_status[mode] register via CSR interface. This returns VL data field data for all 20 virtual lanes.

  3. Set the Physical Lanes for each Remote Virtual Lane:
    Step through the data provided by each Local Virtual lane:
    • Each lane provides a REMOTE_VL and a LOCAL_PL value.

    For each of the 20 possible Remote virtual lanes, set PL[REMOTE_VL] = LOCAL_PL.

    For example, if you read Local Virtual lane 12, and get back REMOTE_VL = 5, LOCAL_PL = 2, that means the data for Virtual lane 5 from the link partner is coming in on our Physical lane 2. You store that as PL[5] = 2.

  4. To calculate PTP timestamps, the MAC uses aligner information from the PCS to translate the timestamp of a random Serdes bit to that of an Alignment Marker bit. This difference is called the Virtual Lane Offset:
    For 100G/50G, the status registers in the register maps provide the Aligner information:
    • ptp_vl_data_hi[19:0]
    • ptp_vl_data_lo[19:0]
    • ptp_lal[4:0] = This register indicates which local lane last received its alignment marker. This register is not used for VL OFFSET calculations

    When a sync_pulse is received, the PCS snapshots its aligner states and stores them in ptp_vl_data_hi and ptp_vl_data_hi. The MAC reads this from CSRs and calculates the bits between bit 0 of the sync block and bit 0 of the last AM received (Virtual Lane Offset).

  5. Calculate the Virtual Lane Offsets for each of the Remote Virtual Lanes in bits:
    For 100GE rate:
    Virtual Lane Offset = sync_pulse to last AM  
   = gb_33_66_occupancy + gb_66_110_occupancy + blk_align_occupancy
   + am_detect_occupancy + am_count - local_lane_adjust
    • gb_33_66_occupency (in PL bits) = ptp_gb33_66_occupancy (from register map)
    • gb_66_110_occupancy (in PL bits) = ptp_gb110_occupancy (from the register map)
    • blk_align_occupancy (in VL bits) = ptp_blk_align_occupancy (from register map) x 5 to convert to PL bits.
    • am_count (in VL blocks) = ptp_am_count (from the register map) x 66b/block x 5 to convert to PL bits
    • local_lane_adjust (in PL bits) = local_vl %5 (This is the bit offset of the local lane’s bit 0 from bit 0 of the interleaved sync block from PHY) 
    For 50GE rate:
   Virtual Lane Offset = sync_pulse to last AM  
  = gb_33_66_occupancy + sep50_occupancy + blk_align_occupancy
  + am_detect_occupancy + am_count - local_lane_adjust
    • gb_33_66_occupancy (in PL bits) = ptp_gb_33_66_occupancy from the register map
    • sep50_occupancy (in PL bits) = ptp_gb110_occupancy from the register map
    • blk_align_occupancy (in VL bits) = ptp_blk_align_occupancy from the register map, x 2 to covert to PL bits
    • am_detect_occupancy (in VL bits) = ptp_am_detect_occupancy from the register map, x2 to convert to PL bits
    • am_count (in VL blocks) = ptp_am_count from the register map, x66b/block x 2 to convert to PL bits
    • local_lane_adjust (in PL bits) = local_vl %2 (This is the bit offset of the local lane’s bit 0 from bit 0 of the interleaved sync block from PHY)
  6. Apply shifts to the offsets for REMOTE_VLs {18..19} to account for the mii_am/mii_data reordering that happens in the PCS MII Decoder. This step is applicable for 50GE-2 and 100GE rates only.
    • Generate vl_offset_bits shifted for each of the REMOTE_VLs.
    • When using RX PTP on data from the RX PCS, shift the times for REMOTE_VLs 18 to 19 by -330 bits:
      vl_offset_bits_shifted[REMOTE_VL] = vl_offset_bits[REMOTE_VL] -330 for REMOTE_VL == {18..19}
vl_offset_bits_shifted[REMOTE_VL] = vl_offset_bits[REMOTE_VL] for REMOTE_VL == {0..17}

      This shift accounts for a shift that is applied by the RX PCS to incoming data.

      For example, if vl_offset_bits[18] == 887, set vl_offset_bits_shifted[18] to 557. If vl_offset_bits[17] == 887, set vl_offset_bits_shifted[17] to 887.

    Note: For 50GE-2 rates, follow same instructions except only apply the shifting to VL3.
  7. Convert the vl_offset_bits to VL_OFFSET (in ns):
    For each REMOTE_VL, VL_OFFSET[REMOTE_VL] = vl_offset_bits_shifted[REMOTE_VL] * RX_UI
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