F-Tile Ethernet Intel® FPGA Hard IP User Guide

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ID 683023
Date 11/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. F-Tile Ethernet Intel® FPGA Hard IP Parameters 4. Functional Description 5. Clocks 6. Resets 7. Interface Overview 8. Configuration Registers 9. Supported Modules and IPs 10. Supported Tools 11. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives 12. Document Revision History for the F-Tile Ethernet Intel® FPGA Hard IP User Guide
1. Overview x
1.1. Ethernet System in F-Tile Overview 1.2. F-Tile Ethernet Intel® FPGA Hard IP Overview
1.2. F-Tile Ethernet Intel® FPGA Hard IP Overview x
1.2.1. Device Family Support 1.2.2. Device Speed Grade Support 1.2.3. Resource Utilization 1.2.4. Round-trip Latency 1.2.5. Release Information
2. Getting Started x
2.1. Installing and Licensing F-Tile Ethernet Intel® FPGA Hard IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Reference and System PLL Clock for your IP Design 2.4. Generated File Structure 2.5. Generating Tile Files 2.6. IP Core Testbenches
2.4. Generated File Structure x
2.4.1. Generating IP-XACT File
4. Functional Description x
4.1. Datapath Description 4.2. F-Tile Ethernet Intel® FPGA Hard IP MAC 4.3. PCS, OTN, and FlexE Modes 4.4. Precision Time Protocol 4.5. Auto-Negotiation and Link Training
4.2. F-Tile Ethernet Intel® FPGA Hard IP MAC x
4.2.1. MAC TX Datapath 4.2.2. MAC RX Datapath 4.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) 4.2.4. Link Fault Signaling 4.2.5. Order of Ethernet Transmission
4.2.1. MAC TX Datapath x
4.2.1.1. TX Preamble, Start, and SFD Insertion 4.2.1.2. Source Address Insertion 4.2.1.3. Length/Type Field Processing 4.2.1.4. Frame Padding 4.2.1.5. Frame Check Sequence (CRC-32) Insertion 4.2.1.6. Inter-Packet Gap Generation and Insertion 4.2.1.7. TX Packing Logic
4.2.2. MAC RX Datapath x
4.2.2.1. RX Preamble Processing 4.2.2.2. RX Strict SFD Checking 4.2.2.3. RX FCS Checking 4.2.2.4. RX Malformed Packet Handling 4.2.2.5. Removing PAD Bytes and FCS Bytes from RX Frames 4.2.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors 4.2.2.7. Inter-Packet Gap
4.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
4.2.3.1. Conditions Triggering XOFF Frame Transmission 4.2.3.2. Conditions Triggering XON Frame Transmission 4.2.3.3. Pause Control and Generation Interface 4.2.3.4. Pause Control Frame Filtering
4.3. PCS, OTN, and FlexE Modes x
4.3.1. PCS Mode 4.3.2. OTN Mode 4.3.3. FlexE Mode
4.4. Precision Time Protocol x
4.4.1. Features 4.4.2. PTP Timestamp Accuracy 4.4.3. PTP Client Flow 4.4.4. RX Virtual Lane Offset Calculation for No FEC Variants 4.4.5. Virtual Lane Order and Offset Values 4.4.6. UI Adjustment 4.4.7. Reference Time Interval 4.4.8. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware) 4.4.9. UI Value and PMA Delay 4.4.10. Routing Delay Adjustment for Advanced Timestamp Accuracy Mode 4.4.11. Routing Delay Adjustment for Basic Timestamp Accuracy Mode
4.4.3. PTP Client Flow x
4.4.3.1. PTP TX Client Flow 4.4.3.2. PTP RX Client Flow
4.4.6. UI Adjustment x
4.4.6.1. TX UI Adjustment 4.4.6.2. RX UI Adjustment
5. Clocks x
5.1. Clock Connections in Single Instance Operation 5.2. Clock Connections in Multiple Instance Operation 5.3. Clock Connections in MAC Asynchronous FIFO Operation 5.4. Clock Connections in PTP-Based Synchronous and Asynchronous Operation 5.5. Clock Connections in Synchronous Ethernet Operation 5.6. Custom Cadence
6. Resets x
6.1. Reset Signals 6.2. Reset Sequence
7. Interface Overview x
7.1. Status Interface 7.2. TX MAC Avalon ST Client Interface 7.3. RX MAC Avalon ST Aligned Client Interface 7.4. TX MAC Segmented Client Interface 7.5. RX MAC Segmented Client Interface 7.6. MAC Flow Control Interface 7.7. PCS Mode TX Interface 7.8. PCS Mode RX Interface 7.9. FlexE and OTN Mode TX Interface 7.10. FlexE and OTN Mode RX Interface 7.11. Custom Rate Interface 7.12. 32-bit Soft CWBIN Counters 7.13. Reconfiguration Interfaces 7.14. Precision Time Protocol Interface
7.2. TX MAC Avalon ST Client Interface x
7.2.1. TX MAC Avalon ST Client Interface with Disabled Preamble Passthrough 7.2.2. TX MAC Avalon ST Client Interface with Enabled Preamble Passthrough 7.2.3. Using MAC Avalon ST skip_crc Signal to Control Source Address, PAD, and CRC Insertion 7.2.4. Using MAC Avalon ST i_tx_error Signal to Mark Packets Invalid
7.3. RX MAC Avalon ST Aligned Client Interface x
7.3.1. RX MAC Avalon ST Client Interface with Disabled Preamble Passthrough 7.3.2. RX MAC Avalon ST Client Interface with Enabled Passthrough and RX CRC Forwarding 7.3.3. RX MAC Adapter Limitations 7.3.4. RX MAC Avalon ST Client Interface Status
7.4. TX MAC Segmented Client Interface x
7.4.1. TX MAC Segmented Client Interface with Disabled Preamble Passthrough 7.4.2. TX MAC Segmented Client Interface with Enabled Preamble Passthrough 7.4.3. Using MAC Segmented skip_crc Signal to Control Source Address, PAD, and CRC Insertion 7.4.4. Using MAC Segmented i_tx_mac_error to Mark Packets Invalid
7.5. RX MAC Segmented Client Interface x
7.5.1. RX MAC Segmented Client Interface with Disabled Preamble Passthrough 7.5.2. RX MAC Segmented Client Interface with Enabled Passthrough and RX CRC Forwarding 7.5.3. RX MAC Segmented Client Interface Status and Errors
7.13. Reconfiguration Interfaces x
7.13.1. Ethernet Reconfiguration Interfaces 7.13.2. Transceiver Reconfiguration Interfaces
7.14. Precision Time Protocol Interface x
7.14.1. Time-of-Day Interface 7.14.2. TX 2-Step Timestamp Interface 7.14.3. TX 1-Step Timestamp Interface 7.14.4. RX Timestamp Interface 7.14.5. PTP Status Interface 7.14.6. PTP Tile Interface
7.14.3. TX 1-Step Timestamp Interface x
7.14.3.1. PTP Field Offset for 1-Step Operation
8. Configuration Registers x
8.1. Ethernet Avalon® Memory-Mapped Interface Address Space 8.2. Transceiver Avalon® Memory-Mapped Interface Address Space
8.1. Ethernet Avalon® Memory-Mapped Interface Address Space x
8.1.1. Ethernet Hard IP Core CSRs 8.1.2. FEC and Transceiver Control and Status Registers
9. Supported Modules and IPs x
9.1. F-Tile Auto-Negotiation and Link Training For Ethernet Intel® FPGA IP 9.2. PTP Tile Adapter
9.1. F-Tile Auto-Negotiation and Link Training For Ethernet Intel® FPGA IP x
9.1.1. Overview 9.1.2. Release Information 9.1.3. Functional Description 9.1.4. Parameters 9.1.5. Clocks and Resets 9.1.6. Registers
9.2. PTP Tile Adapter x
9.2.1. Overview 9.2.2. Clocks, Reset, and Interface Ports 9.2.3. PTP Asymmetry Delay Reconfiguration Interface 9.2.4. PTP Peer-to-Peer MeanPathDelay Reconfiguration Interface
10. Supported Tools x
10.1. F-Tile Channel Placement Tool 10.2. Ethernet Toolkit Overview
10.2. Ethernet Toolkit Overview x
10.2.1. Features
1. Overview
2. Getting Started
3. F-Tile Ethernet Intel® FPGA Hard IP Parameters
4. Functional Description
5. Clocks
6. Resets
7. Interface Overview
8. Configuration Registers
9. Supported Modules and IPs
10. Supported Tools
11. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives
12. Document Revision History for the F-Tile Ethernet Intel® FPGA Hard IP User Guide

7.7. PCS Mode TX Interface

The F-Tile Ethernet Intel® FPGA Hard IP TX client interface in PCS variations employs the Media Independent Interface (MII) protocol.

The client acts as a source and the TX PCS acts as a sink in the transmit direction.

Table 49.  Signals of the MII TX Client InterfaceAll interface signals are clocked by the TX clock. The signal names are standard Avalon® streaming interface signals.

Signal Name

Width

Description

i_tx_mii_d[1023:0]

i_tx_mii_d[511:0]

i_tx_mii_d[255:0]

i_tx_mii_d[127:0]

i_tx_mii_d[63:0]

1024 bits (400GE)

512 bits (200GE)

256 bits (100GE)

128 bits (40GE/50GE)

64 bits(10GE/25GE)

TX MII data. Data must be in MII encoding. i_tx_mii_d[7:0] holds the first byte the IP core transmits on the Ethernet link. i_tx_mii_d[0] holds the first bit the IP core transmits on the Ethernet link.

While the TX MII valid signal has the value of 0 or the alignment marker insertion bit signal has the value of 1, and for one additional clock cycle, you must hold the value of this signal stable, a behavior called freezing the signal value.

i_tx_mii_c[127:0]

i_tx_mii_c[63:0]

i_tx_mii_c[31:0]

i_tx_mii_c[15:0]

i_tx_mii_c[7:0]

128 bits (400GE)

64 bits (200GE)

32 bits (100GE)

16 bits (40GE/50GE)

8 bits(10GE/25GE)

 TX MII control bits. Each bit corresponds to a byte of the TX MII data signal. For example, i_tx_mii_c[0] corresponds to i_tx_mii_d[7:0], i_tx_mii_c[1] corresponds to i_tx_mii_d[15:8], and so on.

If the value of a bit is 1, the corresponding data byte is a control byte. If the value of a bit is 0, the corresponding data byte is data.

i_tx_mii_valid

1 bit Indicates that the TX MII data signal is valid.

You must assert this signal a fixed number of clock cycles after the IP core raises ready signal, and must deassert this signal the same number of clock cycles after the IP core deasserts the ready signal. The number must be in the range of 1–6 clock cycles.

o_tx_mii_ready

1 bit Indicates the PCS is ready to receive new data.

i_tx_mii_am

1 bit Alignment marker insertion bit.
Figure 44. Transmitting Data Using the PCS Mode TX Interface

The figure above shows how to write packets directly to the PCS mode TX interface.

  • The packets are written using MII.
    • Each byte in i_tx_mii_d has a corresponding bit in i_tx_mii_c that indicates whether the byte is a control byte or a data byte; for example, i_tx_mii_c[1] is the control bit for i_tx_mii_d[15:8].
  • i_tx_mii_valid should conform to these conditions:
    • Assert the valid signal only when the ready signal is asserted, and deassert only when the ready signal is deasserted.
    • The two signals can be spaced by a fixed latency between 1 and 6 cycles.
    • When the valid signal deasserts, i_tx_mii_d and i_tx_mii_c must be paused.
  • The byte order for the PCS mode TX interface is opposite of the byte order for the MAC Avalon® streaming interface. Bytes flow from LSB to MSB; the first byte to be transmitted from the interface is i_tx_mii_d[7:0].
  • The bit order for the PCS mode TX interface is the same as the bit order of the MAC client. The first bit to be transmitted from the interface is i_tx_mii_d[0].
Note: The PCS mode TX interface is not SOP aligned. Any legal ordering of packets in MII format is accepted.
Table 50.  Writing a Start Packet Block with Preamble to the PCS Mode TX Interface
MII Data MII Control Ethernet Packet Byte
i_tx_mii_d[7:0] 0xFB i_tx_mii_c[0] 1 Start of Packet
i_tx_mii_d[15:8] 0x55 i_tx_mii_c[1] 0 Preamble
i_tx_mii_d[23:16] 0x55 i_tx_mii_c[2] 0 Preamble
i_tx_mii_d[31:24] 0x55 i_tx_mii_c[3] 0 Preamble
i_tx_mii_d[39:32] 0x55 i_tx_mii_c[4] 0 Preamble
i_tx_mii_d[47:40] 0x55 i_tx_mii_c[5] 0 Preamble
i_tx_mii_d[55:48] 0x55 i_tx_mii_c[6] 0 Preamble
i_tx_mii_d[63:56] 0xD5 i_tx_mii_c[7] 0 SFD
Figure 45. Inserting Alignment MarkersThe following figure shows the timing diagram for a 100G rate and illustrates how to perform alignment marker insertion.

The fabric controls the timing of alignment marker insertion. Alignment markers cannot be delayed without disrupting the Ethernet link. Use valid cycles to count the alignment markers.

For alignment marker counts, you only use valid cycles. When i_tx_mii_valid is low, the alignment marker counters and input data must freeze.

The number of cycles that i_tx_mii_am remains high depends on the interface rate. Refer to the following table for reference:
Table 51.  Alignment Marker Insertion Periods
Ethernet Mode # of VLanes AM Insertion (Blocks/VLane) AM Period (Blocks/VLane) AM Period (Blocks) Client Width (Blocks) Client AM Insertion Cycles Client AM Insertion Period (Cycles)
25G with RS-FEC 1 4 81920 81920 1 4 81920
40G

50G-2 (consortium) (NO RS-FEC)

 4 1 16384 65536 2 2 32768
50G-2 (consortium) (with RS-FEC)

50G-1 (IEEE)

 4 1 20480 81920 2 2 40960
100G 20 1 16384 327680 4 5 81920
200G 8 2 40960 327680 8 2 40960
400G 16 2 40960 655360 16 2 40960

The number of cycles for am period depends on the rate of the interface and whether in simulation or hardware.

In simulation, it is common to use a reduced am period for both sides of the link to increase lock-time speed. Refer to the following tables for simulation with Non-PTP and PTP Enabled Modes:
Table 52.  Alignment Marker Insertion Periods for Simulation with Non-PTP Enabled Modes
Ethernet Mode # of VLanes AM Insertion (Blocks/VLane) AM Period (Blocks/VLane) AM Period (Blocks) Client Width (Blocks) Client AM Insertion Cycles Client AM Insertion Period (Cycles)
25G with RS-FEC 1 4 1280 1280 1 4 1280
40G 4 1 64 256 2 2 128
50G-2 (consortium) (NO RS-FEC) 4 1 256 1024 2 2 512
50G-2 (consortium) (with RS-FEC)

50G-1 (IEEE)

 4 1 320 1280 2 2 640
100G 20 1 256 5120 4 5 1280
200G 8 2 640 5120 8 2 640
400G 16 2 640 10240 16 2 640
Table 53.  Alignment Marker Insertion Periods for Simulation with PTP Enabled modes
Ethernet Mode # of VLanes AM Insertion (Blocks/VLane) AM Period (Blocks/VLane) AM Period (Blocks) Client Width (Blocks) Client AM Insertion Cycles Client AM Insertion Period (Cycles)
25G with RS-FEC 1 4 2560 2560 1 4 2560
50G-2 (consortium) (with RS-FEC)

50G-1 (IEEE)

 4 1 1280 5120 2 2 2560
100G 20 1 512 10240 4 5 2560
200G 8 2 2560 20480 8 2 2560
400G 16 2 2560 40960 16 2 2560

For proper operation, program the MAC, PCS, and optional FEC to use the same am period.

In FEC modes, the TX datapath does not come completely out of reset until at least 2 alignment marker periods passed. You must start driving i_tx_mii_am at the proper interval before o_tx_lanes_stable goes high. You may drive the signal as soon as o_tx_pll_locked has gone high and o_tx_mii_ready starts toggling. When the external custom rate interface is enabled, you must start driving i_custom_cadence. For more information, refer to the Custom Rate Interface.

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