F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 3/11/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.1. Datapath Description

In the transmit direction, the MAC accepts client frames, and inserts inter-packet gap (IPG), preamble, start of frame delimiter (SFD), padding, and CRC bits before passing them to the PHY. You can configure the MAC to accept some of the additions with the client frame. The MAC also updates the TX statistics counters. The PHY encodes the MAC frame as required for reliable transmission over the media to the remote end.

In the receive direction, the PHY passes frames to the MAC. The MAC accepts frames from the PHY, performs checks, updates statistics counters, strips out the CRC, preamble, and SFD, and passes the rest of the frame to the client. In RX preamble pass-through mode, the MAC passes on the preamble and SFD to the client instead of stripping them out. You can configure the MAC to provide the full RX frame at the client interface, the frame with CRC bytes removed, or the frame with CRC and RX PAD bytes removed.

The F-Tile Ethernet Intel® FPGA Hard IP also supports PCS, FlexE, and OTN variations. The PCS variations provide an MII interface to the client and transmit and receive Ethernet packets through a 10-Gbps, 25-Gbps, 50-Gbps, 100-Gbps, 200-Gbps, and 400-Gbps Ethernet PHY implemented in hard IP. The FlexE and OTN variations use PCS66 interface for transmitting and receiving 66b blocks, bypassing the MAC.

The IP core handles the frame encapsulation and flow of data between client logic and an Ethernet network through a 10-Gbps, 25-Gbps, 40-Gbps, 50-Gbps, 100-Gbps, 200-Gbps, and 400-Gbps Ethernet PHY implemented in hard IP, with optional various Forward Error Corrections (FEC).