Visible to Intel only — GUID: bbe1557762871577
Ixiasoft
1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP v22.0.0
1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP v21.0.2
1G/2.5G/5G/10G Multirate Ethernet PHY v21.0.1
1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP v20.1.0
1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP v20.0.0
1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP v19.3.0
1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP v19.1
1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP v18.0
1G/2.5G/5G/10G Multirate Ethernet PHY IP Core v17.1
1G/2.5G/5G/10G Multirate Ethernet PHY v16.0
1G/2.5G/10G Multirate Ethernet PHY v15.1
Visible to Intel only — GUID: bbe1557762871577
Ixiasoft
1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP v19.1
Description | Impact |
---|---|
Renamed the Enable Altera Debug Master Endpoint parameter to Enable Native PHY Debug Master Endpoint as per Intel® rebranding in the Quartus® Prime Pro Edition software. The Quartus® Prime Standard Edition software still uses Enable Altera Debug Master Endpoint. | — |