Intel® MPI Library Developer Reference for Windows* OS

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Date 7/13/2023
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Document Table of Contents
Document Table of Contents x
Intel® MPI Library Developer Reference for Windows* OS
Intel® MPI Library Developer Reference for Windows* OS x
Introduction Command Reference Environment Variable Reference Notices and Disclaimers
Introduction x
Introducing Intel® MPI Library What's New Notational Conventions Related Information User Authorization
Command Reference x
Compiler Commands mpiexec.hydra cpuinfo impi_info mpitune
Compiler Commands x
Compilation Command Options
mpiexec.hydra x
Global Hydra Options Local Hydra Options
mpitune x
mpitune Configuration Options
Environment Variable Reference x
Compilation Environment Variables Hydra Environment Variables I_MPI_ADJUST Family Environment Variables Tuning Environment Variables Main Thread Pinning Environment Variables for Fabrics Control Environment Variables for Memory Policy Control Other Environment Variables
Tuning Environment Variables x
Autotuning
Autotuning x
I_MPI_TUNING_AUTO Family Environment Variables
Main Thread Pinning x
Environment Variables for Main Thread Pinning Interoperability with OpenMP* API
Environment Variables for Fabrics Control x
Communication Fabrics Control Shared Memory Control OFI*-capable Network Fabrics Control
Intel® MPI Library Developer Reference for Windows* OS

cpuinfo

Provides information on processors used in the system.

Syntax

cpuinfo [[-]<options>]

Arguments

<options> Sequence of one-letter options. Each option controls a specific part of the output data.
g

General information about single cluster node shows:

  • the processor product name
  • the number of packages/sockets on the node
  • core and threads numbers on the node and within each package
  • SMT mode enabling
i

Logical processors identification table identifies threads, cores, and packages of each logical processor accordingly.

  • Processor - logical processor number.
  • ThreadId - unique processor identifier within a core.
  • CoreId - unique core identifier within a package.
  • PackageId - unique package identifier within a node.
d

Node decomposition table shows the node contents. Each entry contains the information on packages, cores, and logical processors.

  • Package Id - physical package identifier.
  • Cores Id - list of core identifiers that belong to this package.
  • Processors Id - list of processors that belong to this package. This list order directly corresponds to the core list. A group of processors enclosed in brackets belongs to one core.
c

Cache sharing by logical processors shows information of sizes and processors groups, which share particular cache level.

  • Size - cache size in bytes.
  • Processors - a list of processor groups enclosed in the parentheses those share this cache or no sharing otherwise.
s

Microprocessor signature hexadecimal fields (Intel platform notation) show signature values:

  • extended family
  • extended model
  • family
  • model
  • type
  • stepping
f Microprocessor feature flags indicate what features the microprocessor supports. The Intel platform notation is used.
n

Table shows the following information about NUMA nodes:

  • NUMA Id - NUMA node identifier.
  • Processors - a list of processors in this node.

If the node has no processors, the node is not shown.

A Equivalent to gidcsf
gidc Default sequence
? Utility usage info

Description

The cpuinfo utility prints out the processor architecture information that can be used to define suitable process pinning settings. The output consists of a number of tables. Each table corresponds to one of the single options listed in the arguments table.

NOTE:

The architecture information is available on systems based on the Intel® 64 architecture.

The cpuinfo utility is available for both Intel microprocessors and non-Intel microprocessors, but it may provide only partial information about non-Intel microprocessors.

An example of the cpuinfo output: 

> cpuinfo -gdcs
=====  Processor composition  =====
Processor name    : Intel(R) Xeon(R)  X5570
Packages(sockets) : 2
Cores             : 8
Processors(CPUs)  : 8
Cores per package : 4
Threads per core  : 1
=====  Processor identification  =====
Processor       Thread Id.      Core Id.        Package Id.
0               0               0               0
1               0               0               1
2               0               1               0
3               0               1               1
4               0               2               0
5               0               2               1
6               0               3               0
7               0               3               1
=====  Placement on packages  =====
Package Id.     Core Id.        Processors
0               0,1,2,3         0,2,4,6
1               0,1,2,3         1,3,5,7
=====  Cache sharing  =====
Cache   Size            Processors
L1      32  KB          no sharing
L2      256 KB          no sharing
L3      8   MB          (0,2,4,6)(1,3,5,7)
=====  Processor Signature  =====
 _________ ________ ______ ________ _______ __________
| xFamily | xModel | Type | Family | Model | Stepping |
|_________|________|______|________|_______|__________|
| 00      | 1      | 0    | 6      | a     | 5        |
|_________|________|______|________|_______|__________|
Parent topic: Command Reference
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