Developer Guide and Reference

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ID 767253
Date 10/31/2024
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Document Table of Contents
Document Table of Contents x
Developer Guide and Reference
Developer Guide and Reference x
Intel® oneAPI DPC++/C++ Compiler Introduction Compiler Setup Compiler Reference Compilation Optimization and Programming Compatibility and Portability Notices and Disclaimers
Intel® oneAPI DPC++/C++ Compiler Introduction x
Get Help and Support Related Information
Compiler Setup x
Use the Command Line Use Eclipse Use Microsoft Visual Studio
Use the Command Line x
Specify Component Locations Invoke the Compiler Use the Command Line on Windows File Extensions Use Makefiles for Compilation Use CMake with the Compiler Use Compiler Options Specify Compiler Files Convert Projects to Use a Selected Compiler
Use Eclipse x
Add the Compiler to Eclipse Multiversion Compiler Support Use Cheat Sheets Create a Simple Eclipse Project Makefiles Use Intel Libraries with Eclipse
Use Microsoft Visual Studio x
Create a New Project Use the Intel® oneAPI DPC++/C++ Compiler Select the Compiler Version Specify a Base Platform Toolset Use Property Pages Use Intel® Libraries with Microsoft Visual Studio* Include MPI Support Use Code Coverage in Microsoft Visual Studio* Use Profile Guided Optimization in Microsoft Visual Studio* Optimization Reports in Microsoft Visual Studio* Dialog Box Help
Dialog Box Help x
Use Intel® oneAPI DPC++/C++ Compiler dialog box Hardware Profile-Guided Optimization dialog box Options: Compilers dialog box Options: Intel Libraries for oneAPI dialog box Options: Converter dialog box Options: Optimization Reports dialog box Options: Profile Guided Optimization dialog box Profile Guided Optimization dialog box Options: Code Coverage dialog box Code Coverage dialog box Code Coverage Settings dialog box
Compiler Reference x
C/C++/SYCL Calling Conventions Compiler Options Floating-Point Operations Attributes Intrinsics Libraries Macros Pragmas Syntactic and Semantic Errors
Compiler Options x
Alphabetical Option List General Rules for Compiler Options What Appears in the Compiler Option Descriptions Optimization Options Advanced Optimization Options Code Generation Options Offload Compilation, OpenMP*, and Parallel Processing Options Interprocedural Optimization Options Profile Guided Optimization Options Optimization Report Options Floating-Point Options Inlining Options Output, Debug, and Precompiled Header Options Preprocessor Options Component Control Options Language Options Data Options Compiler Diagnostic Options Compatibility Options Linking or Linker Options Miscellaneous Options Deprecated and Removed Compiler Options Display Option Information Alternate Compiler Options Portability and GCC-Compatible Warning Options
Optimization Options x
fast fbuiltin, Oi foptimize-sibling-calls GF nolib-inline O Od Ofast Os Ot Ox
Advanced Optimization Options x
ffreestanding, Qfreestanding fjump-tables fvec-allow-scalar-stores, Qvec-allow-scalar-stores fvec-peel-loops, Qvec-peel-loops fvec-remainder-loops, Qvec-remainder-loops fvec-with-mask, Qvec-with-mask ipp-link, Qipp-link mno-gather, Qgather- mno-scatter, Qscatter- qactypes, Qactypes qdaal, Qdaal qipp, Qipp qmkl, Qmkl qmkl-ilp64, Qmkl-ilp64 qmkl-sycl-impl, Qmkl-sycl-impl qopt-assume-no-loop-carried-dep, Qopt-assume-no-loop-carried-dep qopt-dword-index-for-array-of-structs, Qopt-dword-index-for-array-of-structs qopt-dynamic-align, Qopt-dynamic-align qopt-for-throughput, Qopt-for-throughput qopt-mem-layout-trans, Qopt-mem-layout-trans qopt-multiple-gather-scatter-by-shuffles, Qopt-multiple-gather-scatter-by-shuffles qopt-prefetch, Qopt-prefetch qopt-prefetch-distance, Qopt-prefetch-distance qopt-prefetch-loads-only, Qopt-prefetch-loads-only qopt-streaming-stores, Qopt-streaming-stores qopt-zmm-usage, Qopt-zmm-usage qtbb, Qtbb unroll, Qunroll vec, Qvec vec-threshold, Qvec-threshold vecabi, Qvecabi
Code Generation Options x
arch ax, Qax Syntax Arguments Default Description IDE Equivalent Alternate Options Examples See Also EH fasynchronous-unwind-tables fcf-protection, Qcf-protection fdata-sections, Gw fexceptions ffunction-sections, Gy fomit-frame-pointer Gd GR guard Gv m, Qm m64, Qm64 m80387 march masm mauto-arch, Qauto-arch mbranches-within-32B-boundaries, Qbranches-within-32B-boundaries mintrinsic-promote, Qintrinsic-promote momit-leaf-frame-pointer mtune, tune regcall, Qregcall x, Qx xHost, QxHost
Offload Compilation, OpenMP*, and Parallel Processing Options x
device-math-lib fintelfpga fiopenmp, Qiopenmp flink-huge-device-code fno-sycl-libspirv fopenmp fopenmp-concurrent-host-device-compile, Qopenmp-concurrent-host-device-compile fopenmp-declare-target-scalar-defaultmap, Qopenmp-declare-target-scalar-defaultmap fopenmp-device-code-split, Qopenmp-device-code-split fopenmp-device-lib fopenmp-device-link, Qopenmp-device-link fopenmp-max-parallel-link-jobs, Qopenmp-max-parallel-link-jobs fopenmp-offload-mandatory, Qopenmp-offload-mandatory fopenmp-target-buffers, Qopenmp-target-buffers fopenmp-target-default-sub-group-size, Qopenmp-target-default-sub-group-size fopenmp-target-loopopt, Qopenmp-target-loopopt fopenmp-target-simd, Qopenmp-target-simd fopenmp-targets, Qopenmp-targets fsycl fsycl-add-default-spec-consts-image fsycl-allow-device-dependencies fsycl-dead-args-optimization fsycl-device-code-split fsycl-device-lib fsycl-device-obj fsycl-device-only fsycl-early-optimizations fsycl-enable-function-pointers fsycl-esimd-force-stateless-mem fsycl-explicit-simd fsycl-force-target fsycl-fp64-conv-emu fsycl-help fsycl-host-compiler fsycl-host-compiler-options fsycl-id-queries-fit-in-int fsycl-instrument-device-code fsycl-link fsycl-max-parallel-link-jobs fsycl-optimize-non-user-code fsycl-pstl-offload fsycl-rdc fsycl-remove-unused-external-funcs fsycl-targets fsycl-unnamed-lambda fsycl-use-bitcode ftarget-compile-fast ftarget-export-symbols ftarget-register-alloc-mode, Qtarget-register-alloc-mode nolibsycl qopenmp, Qopenmp qopenmp-link qopenmp-simd, Qopenmp-simd qopenmp-stubs, Qopenmp-stubs reuse-exe Wno-sycl-strict Xopenmp-target Xs Xsycl-target
Interprocedural Optimization Options x
flto ipo, Qipo
Profile Guided Optimization Options x
fprofile-dwo-dir fprofile-ml-use fprofile-sample-generate fprofile-sample-use
Optimization Report Options x
qopt-report, Qopt-report qopt-report-file, Qopt-report-file qopt-report-names, Qopt-report-names qopt-report-phase, Qopt-report-phase qopt-report-stdout, Qopt-report-stdout
Floating-Point Options x
ffp-accuracy, Qfp-accuracy ffp-contract fimf-absolute-error, Qimf-absolute-error fimf-accuracy-bits, Qimf-accuracy-bits fimf-arch-consistency, Qimf-arch-consistency fimf-domain-exclusion, Qimf-domain-exclusion fimf-max-error, Qimf-max-error fimf-precision, Qimf-precision fimf-use-svml, Qimf-use-svml fma, Qfma fp-model, fp fp-speculation, Qfp-speculation ftz, Qftz pc, Qpc
Inlining Options x
fgnu89-inline finline finline-functions inline-forceinline, Qinline-forceinline
Output, Debug, and Precompiled Header Options x
c debug (Linux*) debug (Windows*) Fa fasm-blocks Fe Fo Fp fsystem-debug fverbose-asm g gdwarf grecord-gcc-switches gsplit-dwarf o S use-msasm Y- Yc Yu Zi, Z7, ZI
Preprocessor Options x
B C D dD, QdD dM, QdM E EP FI H, QH I idirafter imacros iprefix iquote isystem iwithprefix iwithprefixbefore M, QM MD, QMD MF, QMF MG, QMG MM, QMM MMD, QMMD MQ, QMQ MT, QMT nostdinc++ P TP U undef X
Component Control Options x
Qoption
Language Options x
ansi fno-gnu-keywords fno-operator-names fno-rtti fpermissive fshort-enums fsyntax-only, Zs funsigned-char, J std, Qstd strict-ansi vd vmg x (type option) Zc Zg Zp
Data Options x
fcommon fkeep-static-consts, Qkeep-static-consts fmaintain-32-byte-stack-align, Qmaintain-32-byte-stack-align fmath-errno fpack-struct fpic fpie fstack-protector fstack-security-check fvisibility fzero-initialized-in-bss, Qzero-initialized-in-bss GA Gs GS mcmodel Qlong-double
Compiler Diagnostic Options x
w W Wabi Wall Wcheck-unicode-security Wcomment Wdeprecated Werror, WX Werror-all Wextra-tokens Wformat Wformat-security Wmain Wmissing-declarations Wmissing-prototypes Wpointer-arith Wreorder Wreturn-type Wshadow Wsign-compare Wstrict-aliasing Wstrict-prototypes Wtrigraphs Wuninitialized Wunknown-pragmas Wunused-function Wunused-variable Wwrite-strings
Compatibility Options x
gcc-toolchain vmv
Linking or Linker Options x
F (Windows*) fixed fortlib fuse-ld l L LD link MD MT nodefaultlibs no-intel-lib, Qno-intel-lib nostartfiles nostdlib pie pthread shared shared-intel shared-libgcc static static-intel static-libgcc static-libstdc++ T u (Linux*) v Wa Wl Wp Xlinker Zl
Miscellaneous Options x
dryrun dumpmachine dumpversion fpreview-breaking-changes help MP nologo save-temps, Qsave-temps showIncludes sox sysroot Tc TC Tp version
Floating-Point Operations x
Programming Tradeoffs in Floating-Point Applications Floating-Point Optimizations Denormal Numbers Floating-Point Environment Set the FTZ and DAZ Flags Tuning Performance IEEE Floating-Point Operations
Attributes x
align align_value allow_cpu_features code_align const cpu_dispatch, cpu_specific target
Libraries x
Create Libraries Use Intel Shared Libraries Manage Libraries Redistribute Libraries When Deploying Applications Resolve References to Shared Libraries Redistributable Library Considerations Intel's Memory Allocator Library SIMD Data Layout Templates Intel® C++ Class Libraries Intel's C++ Asynchronous I/O Extensions for Windows IEEE 754-2008 Binary Floating-Point Conformance Library Intel's Numeric String Conversion Library
SIMD Data Layout Templates x
Function Calls and Containers User-Level Interface Examples
Function Calls and Containers x
Construct an n_container Bounds
User-Level Interface x
SDLT Primitives soa1d_container aos1d_container n_container Bounds Accessors Proxy Objects Number Representation Indexes Convenience and Correctness
aos1d_container x
access_by
n_container x
Layouts Shape make_ n_container template function extent_d template function
Shape x
n_extent_generator
Bounds x
bounds_t sdlt::bounds Template Function n_bounds_t n_bounds_generator bounds_d Template Function
Accessors x
soa1d_container::accessor and aos1d_container::accessor soa1d_container::const_accessor and aos1d_container::const_accessor Accessor Concept
Proxy Objects x
Proxy ConstProxy
Number Representation x
aligned_offset fixed_offset
Indexes x
linear_index n_index_t n_index_generator index_d template function
Convenience and Correctness x
max_val min_val
Examples x
Efficiency with Structure of Arrays Example Complex SDLT Primitive Construction Example Forward Dependency Example Use of Offsets and Methods on a SDLT Primitive Example RGB to YUV Conversion Example
Intel® C++ Class Libraries x
C++ Classes and SIMD Operations Capabilities of C++ SIMD Classes Integer Vector Classes Floating-Point Vector Classes Classes Quick Reference Programming Example Intel's valarray Implementation
Integer Vector Classes x
Terms and Syntax Rules for Operators Assignment Operator Logical Operators Addition and Subtraction Operators Multiplication Operators Shift Operators Comparison Operators Conditional Select Operators Debug Operations Unpack Operators Pack Operators Clear MMX™ State Operator Integer Functions for Intel® Streaming SIMD Extensions Conversions between Fvec and Ivec
Floating-Point Vector Classes x
Fvec Syntax and Notation Data Alignment Conversions Constructors and Initialization Arithmetic Operators Minimum and Maximum Operators Logical Operators Compare Operators Conditional Select Operators for Fvec Classes Cacheability Support Operators Debug Operations Load and Store Operators Unpack Operators Move Mask Operators
Intel's C++ Asynchronous I/O Extensions for Windows x
Intel's C++ Asynchronous I/O Library for Windows Intel's C++ Asynchronous I/O Class for Windows
Intel's C++ Asynchronous I/O Library for Windows x
aio_read aio_write Example for aio_read and aio_write Functions aio_suspend Example for aio_suspend Function aio_error aio_return Example for aio_error and aio_return Functions aio_fsync aio_cancel Example for aio_cancel Function lio_listio Example for lio_listio Function Asynchronous I/O Function Errors
Intel's C++ Asynchronous I/O Class for Windows x
Template Class async_class get_last_operation_id wait get_status get_last_error get_error_operation_id stop_queue resume_queue clear_queue Example for Using async_class Template Class
IEEE 754-2008 Binary Floating-Point Conformance Library x
Intel® IEEE 754-2008 Binary Floating-Point Conformance Library and Usage Function List Homogeneous General-Computational Operations Functions General-Computational Operation Functions Quiet-Computational Operations Functions Signaling-Computational Operations Functions Non-Computational Operations Functions
Intel's Numeric String Conversion Library x
Use Intel's Numeric String Conversion Library Function List
Macros x
ISO Standard Predefined Macros Additional Predefined Macros Use Predefined Macros to Specify Intel® Compilers
Pragmas x
Intel-Specific Pragma Reference Supported OpenMP* Pragmas Pragmas Compatible with Other Compilers
Intel-Specific Pragma Reference x
block_loop/noblock_loop distribute_point inline, noinline, forceinline ivdep loop_count nofusion novector omp target variant dispatch ompx prefetch data prefetch/noprefetch unroll/nounroll unroll_and_jam/nounroll_and_jam vector
Compilation x
Compilation Overview Supported Environment Variables Pass Options to the Linker Specify Alternate Tools Use Configuration Files Use Response Files Global Symbols and Visibility Attributes for Linux* Save Compiler Information in Your Executable Link Debug Information Ahead of Time Compilation Device Offload Compilation Considerations Use a Third-Party Compiler as a Host Compiler for SYCL Code
Optimization and Programming x
OpenMP* Support SYCL* Support Compiler Sanitizers Intel® oneAPI Level Zero Vectorization Instrumented Profile-Guided Optimization Hardware Profile-Guided Optimization High-Level Optimization Interprocedural Optimization Methods to Optimize Code Size Optimization Reports Compiler Math Library SYCL* Device Library
OpenMP* Support x
Add OpenMP* Support Parallel Processing Model Worksharing Using OpenMP* Control Thread Allocation OpenMP* Library Support OpenMP* Contexts OpenMP* Offloading SPMD/SIMT and SIMD Models OpenMP* Advanced Issues OpenMP* Implementation-Defined Behaviors OpenMP* Examples
OpenMP* Library Support x
OpenMP* Runtime Library Routines Intel® Compiler Extension Routines to OpenMP* OpenMP* Support Libraries Use the OpenMP* Libraries Thread Affinity Interface OpenMP* Memory Spaces and Allocators
OpenMP* Contexts x
OpenMP* Context Selectors Score and Match Context Selectors
SYCL* Support x
SYCL* Extensions Redistribute Your SYCL* Application CUDA* to SYCL* Migration
Intel® oneAPI Level Zero x
Intel® oneAPI Level Zero Switch Intel® oneAPI Level Zero Backend Specification Programming with the Intel® oneAPI Level Zero Backend
Vectorization x
Automatic Vectorization Explicit Vector Programming
Automatic Vectorization x
Vectorization Programming Guidelines Use Automatic Vectorization Vectorization and Loops Loop Constructs
Explicit Vector Programming x
User-Mandated or SIMD Vectorization SIMD-Enabled Functions SIMD-Enabled Function Pointers Function Annotations and the SIMD Directive for Vectorization Explicit SIMD SYCL Extension
Interprocedural Optimization x
Use Interprocedural Optimization Performance Considerations Create a Library from IPO Objects Inline Expansion of Functions
Compiler Math Library x
Use the Compiler Math Library Math Function List Trigonometric Functions Hyperbolic Functions Exponential Functions Special Functions Nearest Integer Functions Remainder Functions Miscellaneous Functions Complex Functions C99 Macros
SYCL* Device Library x
Basic Arithmetic Operations and Simple Math Functions IMF Transcendental Math Functions
Basic Arithmetic Operations and Simple Math Functions x
Simple Integer Math Functions Basic Integer Arithmetic Operations Simple Arithmetic Operations with Rounding Mode Type Casting Functions for Floating-Point Numbers Type Casting Functions for Half-Precision Types Type Casting Functions for bfloat16 Type Simple Half-Precision Arithmetic Math Functions Half-Precision Comparison Functions
IMF Transcendental Math Functions x
IMF Device Library Usage Example IMF Device Library Function List IMF Device Library Trigonometric Functions IMF Device Library Hyperbolic Functions IMF Device Library Exponential Functions IMF Device Library Logarithmic Functions IMF Device Library Power Functions IMF Device Library Special Functions IMF Device Library Rounding Functions IMF Device Library Miscellaneous Functions
Compatibility and Portability x
Standards Conformance GCC Compatibility and Interoperability Microsoft Compatibility Port from Microsoft Visual C++* to the Intel® oneAPI DPC++/C++ Compiler Port from GCC* to the Intel® oneAPI DPC++/C++ Compiler
Port from Microsoft Visual C++* to the Intel® oneAPI DPC++/C++ Compiler x
Modify Your makefile Other Considerations
Port from GCC* to the Intel® oneAPI DPC++/C++ Compiler x
Modify Your makefile Other Considerations
Developer Guide and Reference

ax, Qax

Tells the compiler to generate multiple, feature-specific auto-dispatch code paths for Intel® processors if there is a performance benefit.

Syntax

Linux:

-axcode

Windows:

/Qaxcode

Arguments

code

Indicates to the compiler a feature set that it may target, including which instruction sets it may generate. The following descriptions refer to Intel® Streaming SIMD Extensions (Intel® SSE) and Supplemental Streaming SIMD Extensions (SSSE). Possible values are:

ALDERLAKE
AMBERLAKE
BROADWELL
CANNONLAKE
CASCADELAKE
COFFEELAKE
COOPERLAKE
GOLDMONT
GOLDMONT-PLUS
HASWELL
ICELAKE-CLIENT (or ICELAKE)
ICELAKE-SERVER
IVYBRIDGE
KABYLAKE
ROCKETLAKE
SANDYBRIDGE
SAPPHIRERAPIDS
SILVERMONT
SKYLAKE
SKYLAKE-AVX512
TIGERLAKE
TREMONT
WHISKEYLAKE

May generate instructions for processors that support the specified Intel® processor or microarchitecture code name.

Keyword ICELAKE is deprecated and may be removed in a future release.

COMMON-AVX512

May generate Intel® Advanced Vector Extensions 512 (Intel® AVX-512) Foundation instructions, Intel® AVX-512 Conflict Detection Instructions (CDI), as well as the instructions enabled with CORE-AVX2.

CORE-AVX512

May generate Intel® Advanced Vector Extensions 512 (Intel® AVX-512) Foundation instructions, Intel® AVX-512 Conflict Detection Instructions (CDI), Intel® AVX-512 Doubleword and Quadword Instructions (DQI), Intel® AVX-512 Byte and Word Instructions (BWI) and Intel® AVX-512 Vector Length extensions, as well as the instructions enabled with CORE-AVX2.

CORE-AVX2

May generate Intel® Advanced Vector Extensions 2 (Intel® AVX2), Intel® AVX, SSE4.2, SSE4.1, SSE3, SSE2, SSE, and SSSE3 instructions for Intel® processors.

CORE-AVX-I

May generate Float-16 conversion instructions and the RDRND instruction, Intel® Advanced Vector Extensions (Intel® AVX), Intel® SSE4.2, SSE4.1, SSE3, SSE2, SSE, and SSSE3 instructions for Intel® processors.

AVX

May generate Intel® Advanced Vector Extensions (Intel® AVX), Intel® SSE4.2, SSE4.1, SSE3, SSE2, SSE, and SSSE3 instructions for Intel® processors.

SSE4.2

May generate Intel® SSE4.2, SSE4.1, SSE3, SSE2, SSE, and SSSE3 instructions for Intel processors.

SSE4.1

May generate Intel® SSE4.1, SSE3, SSE2, SSE, and SSSE3 instructions for Intel® processors.

ATOM_SSE4.2

May generate MOVBE instructions for Intel® processors, depending on the setting of option -minstruction (Linux) or /Qinstruction (Windows). May also generate Intel® SSE4.2, SSE3, SSE2, and SSE instructions for Intel processors. Optimizes for Intel Atom® processors that support Intel® SSE4.2 and MOVBE instructions.

ATOM_SSSE3

May generate MOVBE instructions for Intel® processors, depending on the setting of option -minstruction (Linux) or /Qinstruction (Windows). May also generate SSSE3, Intel® SSE3, SSE2, and SSE instructions for Intel processors. Optimizes for Intel Atom® processors that support Intel® SSE3 and MOVBE instructions.

SSSE3

May generate SSSE3 instructions and Intel® SSE3, SSE2, and SSE instructions for Intel® processors.

SSE3

May generate Intel® SSE3, SSE2, and SSE instructions for Intel® processors.

You can specify more than one code value. When specifying more than one code value, each value must be separated with a comma. See the Examples section below.

Default

OFF

No auto-dispatch code is generated. Feature-specific code is generated and is controlled by the setting of the following compiler options:

  • Linux*: -march and -x

  • Windows*: /arch and /Qx

Description

This option tells the compiler to generate multiple, feature-specific auto-dispatch code paths for Intel® processors if there is a performance benefit. It also generates a baseline code path. The Intel feature-specific auto-dispatch path is usually more optimized than the baseline path. Other options, such as O3, control how much optimization is performed on the baseline path.

The baseline code path is determined by the architecture specified by options -march or -x (Linux*) or options /arch or /Qx (Windows*). While there are defaults for the [Q]x option that depend on the operating system being used, you can specify an architecture and optimization level for the baseline code that is higher or lower than the default. The specified architecture becomes the effective minimum architecture for the baseline code path.

If you specify both the [Q]ax and [Q]x options, the baseline code will only execute on Intel® processors compatible with the setting specified for the [Q]x.

If you specify both the -ax and -march options (Linux) or the /Qax and /arch options (Windows), the baseline code will execute on non-Intel® processors compatible with the setting specified for the -march or /arch option.

A Non-Intel® baseline and an Intel® baseline have the same set of optimizations enabled, and the default for both is SSE4.2 for x86-based architectures.

The [Q]ax option tells the compiler to find opportunities to generate separate versions of functions that take advantage of features of the specified instruction features.

If the compiler finds such an opportunity, it first checks whether generating a feature-specific version of a function is likely to result in a performance gain. If this is the case, the compiler generates both a feature-specific version of a function and a baseline version of the function. At runtime, one of the versions is chosen to execute, depending on the Intel® processor in use. In this way, the program can benefit from performance gains on more advanced Intel processors, while still working properly on older processors and non-Intel processors. A non-Intel processor always executes the baseline code path.

You can use more than one of the feature values by combining them. For example, you can specify -axSSE4.1,SSSE3 (Linux) or /QaxSSE4.1,SSSE3 (Windows).

NOTE:

This option only applies to host compilation. When offloading is enabled, it does not impact device-specific compilation.

NOTE:

When using the icx compiler, if you experience any program failure when using option -ax during this release, please remove the option to see if that solves the problem. If that action solved the problem, please report a bug.

IDE Equivalent

Visual Studio: Code Generation > Add Processor-Optimized Code Path

Eclipse: Code Generation > Add Processor-Optimized Code Path

Alternate Options

None

Examples

The following shows an example of how to specify this option: 

icx -axSKYLAKE file.cpp            ! Linux* systems
icx /QaxSKYLAKE file.cpp           ! Windows* systems

The following shows an example of how to specify more than one code value: 

icx -axSKYLAKE,BROADWELL file.cpp    ! Linux* systems
icx /QaxBROADWELL,SKYLAKE file.cpp   ! Windows* systems

Note that the comma-separated list must have no spaces between the names.

Parent topic: Code Generation Options

See Also

x, Qx compiler option
xHost, QxHost compiler option
march compiler option
arch compiler option
m compiler option
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