Intel® MEI Commands for Accessing Intel® Platform Service Record (Intel® PSR) Information and State

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More details on the usages of this interface can be found in the Platform Service Record sample (in the High-Level API kit) and the Platform Service Record Overview.

Intel® Platform Service Record (Intel®PSR) Intel® MEI Messages

Guid = ED6703FA-D312-4E8B-9DDD-2155BB2DEE65

The messages in this section are supported by the Intel Platform Service Record (Intel PSR) dynamic client.

Intel PSR messages are supported when the Intel PSR feature is supported by Intel CSME.

Information:

TxBufferSize = 0x2000
RxBufferSize = 0x2000
MaxClients = 1
ClientId = 4

 

PSR_HECI_GET_LOG_STATE

Description

Get Intel PSR log state.

Request

typedef struct
{
    PSR_HECI_HEADER                    Header;
}  PSR_HECI_GET_LOG_STATE_Request;
Field Name Field Name Description
Header PSR_HECI_HEADER Request header

 

Response

typedef struct
{
    PSR_HECI_HEADER                    Header;
    PSR_STATUS                         Status;
    PSR_LOG_STATE                      psrLogState;
    PSR_AVAILABILITY                   psrAvailabilityStatus;
}  PSR_HECI_GET_LOG_STATE_Response;
Field Name Field Type Description

Header

PSR_HECI_HEADER

Response header.

Status

PSR_STATUS

Status.
Expected result values:
PSR_STATUS_SUCCESS - command succeeded.
PSR_STATUS_INVALID_INPUT_PARAMETER - invalid command format.

psrLogState

PSR_LOG_STATE

PSR log state

psrAvailabilityStatus

PSR_AVAILABILITY

Indicates whether Intel PSR is available

 

PSR_HECI_PLATFORM_SERVICE_RECORD_GET

Description

Retrieve the signed Intel  PSR with all the logged information.

Request

typedef struct
{
    PSR_HECI_HEADER                    Header;
    UINT8[20]                          userNonce;
}  PSR_HECI_PLATFORM_SERVICE_RECORD_GET_Request;

Field Name

Field Type

Description

Header

PSR_HECI_HEADER

Request header.

userNonce

UINT8[20]

Nonce created by the user

Response

typedef struct
{
    PSR_HECI_HEADER                    Header;
    PSR_STATUS                         Status;
    PSR_LOG_STATE                      psrLogState;
    PSR_VERSION                        psrVersion;
    PSR_RECORD                         PlatformServiceRecord;
    UINT8[SHA_512_KEY_SIZE]            psrHash;
    UINT8[20]                          userNonce;
    UINT8[20]                          csmeNonce;
    FW_VERSION                         fwVersion;
    SIGNING_MECHANISM                  signingMechanism;
    UINT8[512]                         signature;
    UINT16[4]                          certificateLengths;
    UINT8[3000]                        certificates;
}  PSR_HECI_PLATFORM_SERVICE_RECORD_GET_Response;
Field Name Field Type Description
Header PSR_HECI_HEADER Response header

Status

PSR_STATUS

Status.
Expected result values:
PSR_STATUS_SUCCESS - command succeeded.
PSR_STATUS_INVALID_INPUT_PARAMETER - invalid command format.
PSR_STATUS_UPID_DISABLED – Intel UPID is disabled,
log cannot be retrieved
PSR_STATUS_INTERNAL_ERROR - internal error.

psrLogState

PSR_LOG_STATE

The Intel PSR log state

psrVersion

PSR_VERSION

PSR protocol version

PlatformServiceRecord

PSR_RECORD

Intel PSR log

psrHash

UINT8[SHA_512_KEY_SIZE]

Hash of the Intel PSR log

userNonce

UINT8[20]

Nonce created by the user

csmeNonce

UINT8[20]

Nonce created by Intel PSR firmware

fwVersion

FW_VERSION

Firmware version of the system

signingMechanism

SIGNING_MECHANISM

Signature mechanism used to hash and sign the Intel PSR log

signature

UINT8[512]

The Signature of the Intel PSR log. Signed over:
Hash(H(psrLog) || userNonce || csmeNonce || FWVersion || SignatureMechanism)

certificateLengths

UINT16[4]

An array containing the lengths of the certificates
which are stored in the certificates field in sequence.

certificates

UINT8[3000]

The On-Die CA certificate chain used for signing the Intel PSR log

 

 

PSR_HECI_HEADER

Description

Header for Intel PSR command.

Definition

typedef struct
{
    UINT8                              Command;
    UINT8                              Reserved;
    UINT16                             Length;
}  PSR_HECI_HEADER;

Field Description

Field Name Field Type Description
Command UINT8

The command code.

Command

Command Code

PSR_HECI_GET_LOG_STATE

0xb

PSR_HECI_PLATFORM_SERVICE_RECORD_GET

0xa

Reserved UINT8  
Length UINT16 Total length not including the message header.

 

PSR_STATUS

Definition

typedef enum
{
      PSR_STATUS_SUCCESS                       = 0,
      PSR_STATUS_FEATURE_NOT_SUPPORTED         = 1,
      PSR_STATUS_UPID_DISABLED                 = 2,
      PSR_STATUS_ACTION_NOT_ALLOWED            = 3,
      PSR_STATUS_INVALID_INPUT_PARAMETER       = 4,
      PSR_STATUS_INTERNAL_ERROR                = 5,
      PSR_STATUS_NOT_ALLOWED_AFTER_EOP         = 6,
}   PSR_STATUS;

Note: sizeof(enum) is sizeof(UINT32) = 4 bytes.

PSR_LOG_STATE

Definition

typedef enum
{
      PSR_LOG_STATE_NOT_STARTED                = 0,
      PSR_LOG_STATE_STARTED                    = 1,
      PSR_LOG_STATE_STOPPED                    = 2,
}   PSR_LOG_STATE;

Please note: sizeof(enum) is sizeof(UINT32) = 4 bytes.

Item Descriptions

Item Name

Description

PSR_LOG_STATE_NOT_STARTED

Intel PSR logging has not begun.

PSR_LOG_STATE_STARTED

Intel PSR logging was started and is currently running.

PSR_LOG_STATE_STOPPED

Intel PSR logging was stopped due to a critical event.

PSR_AVAILABILITY

Definition

typedef enum
{
      PSR_IS_AVAILABLE                         = 0,
      UPID_IS_DISABLED                         = 1,
}   PSR_AVAILABILITY;

Please note: sizeof(enum) is sizeof(UINT32) = 4 bytes.

Item Descriptions

Item Name

Description

PSR_IS_AVAILABLE

Intel PSR is available.

UPID_IS_DISABLED

Intel PSR is unavailable because Intel UPID is disabled.

PSR_VERSION

Definition

typedef struct
{
    UINT16                             Major;
    UINT16                             Minor;
}  PSR_VERSION;

Description

Intel PSR protocol version

PSR_RECORD (Intel PSR 1.0)

Definition

typedef struct
{
    UINT8[16]                          PSRID;
    UINT8[64]                          UPID;
    UINT8[1284]                        genesisInfo;
    UINT8[64]                          ledgerInfo;
    UINT32                             eventCount;
    UINT8[1200]                        eventsInfo;
}  PSR_RECORD;

Description

Intel PSR log

Field Description

Field Name

Field Type

Description

PSRID

UINT8[16]

16 bytes containing the Intel PSR UUID.

UPID

UINT8[64]

64 bytes containing the platform Intel UPID.

genesisInfo

UINT8[1284]

Array containing genesis information: genesis date and OEM information.

ledgerInfo

UINT8[64]

Array containing ledger information: counters with power states and power transition information.

eventCount

UINT32

Number of events in the events array.

eventsInfo

UINT8[1200]

Array containing critical events that were logged by Intel PSR.

 

PSR_RECORD (Intel PSR 2.0)

Definition

typedef struct
{
    UINT8[16]                          PSRID;
    UINT8[64]                          UPID;
    UINT8[1284]                        genesisInfo;
    UINT8[32]                          capabilities;
    UINT8[64]                          ledgerInfo;
    UINT32                             eventCount;
    UINT8[1200]                        eventsInfo;
}  PSR_RECORD;

Description

Platform Service Record log

Field Description

Field Name

Field Type

Description

PSRID

UINT8[16]

16 bytes containing the PSR UUID.

UPID

UINT8[64]

64 bytes containing the platform Intel UPID.

genesisInfo

UINT8[1284]

Array containing genesis information: genesis date and OEM information.

capabilities UINT8[32] Array containing PSR capability section

ledgerInfo

UINT8[128]

Array containing ledger information: counters with power states and power transition information.

eventCount

UINT32

Number of events in the events array.

eventsInfo

UINT8[1200]

Array containing critical events that were logged by PSR.

 

genesisInfo

Array containing genesis information: genesis date and OEM information

Field Name Field Type

Genesis Date

UINT8[8]
OEM UINT8[64]
OEM Make UINT8[64]
OEM Model UINT8[64]

Manufacturing Country of Origin

UINT8[64]
OEM DAta UINT8[1024]

 

capabilities

Array containing the PSR capability section

Byte Number Meaning Values
0 CHASSIS INTRUSION 0- Not supported,1-supported
1 EXCESSIVE TEMPERATURE 0- Not supported,1-supported
2 SHOCK DETECTION 0- Not supported,1-supported
3 Remote Platform Erase 0- Not supported,1-supported
4 Local Platform Erase 0- Not supported,1-supported
5-31 Reserved  

 

ledgerInfo

Array containing ledger information: counters with power states and power transition information.

32 counters, 4 bytes each

Counter Number Meaning
0 Number of seconds in S0
1 Number of S0 to S5 transitions
2 Number of S0 to S4 transitions
3 Number of S0 to S3 transitions
4 Number of warm resets
5 Number of boots, when PSR succeeded in registering to get excessive shock events from ISH
6 Number of Intel CSE resets
7-15 Reserved
16 Number of PRTC failures
17 Number of recovery events
18 Number of DAM events
19 Number of Unlock events
20 Number of SVN increase events
21-23 Reserved
24 Number of excessive shock events
25 Number of excessive temperature events
26-31 Reserved

 

 

eventsinfo

Array containing critical events logged by the PSR.

Structure of eventsinfo:

Item Size (bytes)
Number of events 4
Event 1...100 12 bytes for each event

 

Structure of each event:

Field Size (bytes) Value
Event ID 1  

Event sub ID (PSR 2.0. Reserved in PSR 1.0)

3 Event specific
Time stamp 4  
Reserved 4  

 

 

 

FW_VERSION

Description

Firmware version.

Definition

typedef struct
{
    UINT16                             Major;
    UINT16                             Minor;
    UINT16                             Hotfix;
    UINT16                             Build;
}  FW_VERSION;

Field Description

Field Name

Field Type

Description

Major

UINT16

Major version.

Minor

UINT16

Minor version.

Hotfix

UINT16

Hotfix version.

Build

UINT16

Build number.

SIGNING_MECHANISM

Definition

typedef enum
{
      ECDSA384_WITH_SHA384                     = 0,
}   SIGNING_MECHANISM;

Please note: sizeof(enum) is sizeof(UINT32) = 4 bytes.

Item Descriptions

Item Name

Description

ECDSA384_WITH_SHA384

ODCA signing algorithm with SHA384.

SHA_512_KEY_SIZE

Definition

#define  SHA_512_KEY_SIZE                        64