Intel Agilex® 7 FPGA – I/O PLL Reconfiguration Design Example

Intel Agilex® 7 FPGA – I/O PLL Reconfiguration Design Example

714741
12/17/2022
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Introduction

This design example uses an Intel Agilex® 7 FPGA to demonstrate the implementation of the following three different I/O phase-locked loop (PLL) reconfiguration options using the IOPLL Reconfig Intel® FPGA IP core: (1) .mif streaming (2) Advanced mode (3) Clock gating This design example consists of the IOPLL, IOPLL Reconfig, In-System Sources & Probes, and Reset Release Intel FPGA IP cores.

Development Kit

Intel Agilex® 7 FPGA F-Series Transceiver-SoC Development Kit DK-SI-AGF014E3ES

Design Details

Device Family

Intel Agilex® 7 FPGAs and SoC FPGAs F-Series
Quartus Edition

Intel® Quartus® Prime Pro Edition
Quartus Version

19.4
IP Cores (5)
IP Core IP Core Category
Altera IOPLL Reconfig PLL
Top level generated instrumentation fabric Debug & Performance
Altera SignalTap II Agent Debug and Performance
Altera IOPLL ClocksPLLsResets
Altera In-System Sources & Probes SimulationDebugVerification

Detailed Description

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)


Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.


The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.


Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.



Prepare the design template in the Quartus Prime software command-line


At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par


Once the process completes, then type:

quartus_sh --platform -name <project>



Note:

* ACDS Version: 19.4.0 Pro


Development Kit

Intel Agilex® 7 FPGA F-Series Transceiver-SoC Development Kit DK-SI-AGF014E3ES

Design Details

Device Family

Intel Agilex® 7 FPGAs and SoC FPGAs F-Series
Quartus Edition

Intel® Quartus® Prime Pro Edition
Quartus Version

19.4