Introduction
This design example uses a Intel Agilex® 7 FPGA to demonstrate the implementation of the following three different I/O PLL reconfiguration option using the IOPLL Reconfig IP core. (1) .mif streaming (2) Advanced mode (3) Clock gating This design example consists of the IOPLL IP core, IOPLL Reconfig IP core, In-System Sources & Probes Intel FPGA IP core and Reset Release Intel FPGA IP.
IP Cores
(4)
| IP Core | IP Core Category |
|---|---|
| IOPLL Intel FPGA IP | Other |
| IOPLL Reconfig Intel FPGA IP | Other |
| In-System Sources & Probes Intel FPGA IP | Other |
| Reset Release Intel FPGA IP | Other |
Detailed Description
This design example uses a AGFB014R24A2E2V device to demonstrate the implementation of the following three different I/O PLL reconfiguration option using the IOPLL Reconfig IP core.
• .mif streaming
• Advanced mode
• Clock gating