IEEE 1532 Programming

Introduction

The IEEE 1532 in-system programmability (ISP) standard aims to simplify manufacturing support for ISP devices. The IEEE 1532 specification enables concurrent in-system programming of multiple devices minimizing production programming times. The standard builds on the 1149.1 JTAG boundary-scan architecture standard by addressing both silicon and software issues to create a simplified and homogeneous ISP environment. The standard specifies a common software platform for programming a variety of device types, including memory devices and programmable logic devices (PLDs). It enables common programming operation for all IEEE 1532-compliant devices on a system board.

The IEEE 1532 standard is complementary to the JEDEC-approved Jam Standard Test and Programming Language (STAPL). The IEEE 1532 standard is a hardware standard that defines the actual ISP algorithm for each device, while Jam STAPL is a software standard that defines the file format that stores the programming information for the chain of devices.

Documentation

• AN 39: IEEE 1149.1 JTAG Boundary-Scan Testing in Legacy FPGAs
• JTAG and In-System Programmability in MAX® V Devices - MAX V Device Handbook

Related Links

• FPGA BSDL Support
• FPGA Device and Product Support Collection
• FPGA Documentation
• FPGA Support Resources