Power Supply Integrity

Proper bypassing and decoupling techniques improve overall power supply signal integrity, which is important for reliable design operation. These techniques become more significant with increased power supply current requirements as well as increased distance from the power supply to the point-of-load (generally the FPGA or CPLD device). The type of bypassing and decoupling techniques designers should consider depends on the system design and board requirements.

When an output buffer changes state, e.g. driving an output pin from a logical high to a logical low, the output structure momentarily presents a low impedance path across the structure from power supply rail to ground. This output transition causes the output to charge or discharge, requiring that current must be immediately available on the output load to reach the required voltage level. Bypass capacitors locally provide the stored energy required for this current transient.

The transient response for this energy storage system must cover a large frequency and load range. Therefore, a storage system should be composed of a variety of capacitor types. Small capacitors with low series inductance can provide fast current for high-frequency transitions. Large capacitors continue to supply current after the high-frequency capacitors have been depleted of their energy stores. Figure 1 shows a typical energy storage system designed for large frequency and load ranges. Typical designs require capacitors with frequencies ranging from 1 KHz to 500 MHz in three ranges:

• 0.001 to 0.1 µF
• 47 to 100 µF
• 470 to 3,300 µF

Figure 1. Typical Energy Storage System.

The amount of logic used in the device and output switching requirements define decoupling requirements. Additional decoupling capacitance is needed as the number of I/O pins and the capacitive load on the pins increases. Designers should add as many 0.2 µF power-supply decoupling capacitors as possible to the V_CCINT, V_CCIO, and ground pins/planes. Ideally, these small capacitors should be located as close as possible to the device. Designers can decouple each V_CCINT or V_CCIO and ground pin pair with a 0.2-µF capacitor. If a design uses high-density packages such as ball grid array (BGA) packages, it may be difficult to use one decoupling capacitor per V_CCINT / V_CCIO and ground pin pair. In such cases, designers make every effort to use as many decoupling capacitors as allowed by the layout. Decoupling capacitors should have a good frequency response, such as monolithic-ceramic capacitors.

Capacitor Choice & Placement

Proper placement and location are very important for high-frequency capacitors (0.001 to 0.1 µF low inductance ceramic chip). Designers should minimize trace lengths when possible to reduce the inductance in the path from capacitor terminals to the device power pins. This includes paths that go through a solid ground or power plane (V_CCINT or V_CCIO) where the inductance of one inch of solid copper plane is about 1 nH. Bypass capacitor vias should route directly to ground, V_CCINT, or V_CCIO planes. Other capacitor types (47 to 100 µF medium-frequency and 470 to 3,300 µF low-frequency capacitors) are referred to as “bulk” capacitance and can be mounted anywhere on the board. Designers should, however, locate bulk capacitance as close to the device as possible. Place V_CCINT or V_CCIO high-frequency bypass capacitors within one centimeter of the associated V_CCINT or V_CCIO pin on the PCB. V_CCINT or V_CCIO medium-frequency bypass capacitors should be placed within 3 cm of V_CCINT or V_CCIO pins.

V_CCINT Bypass Capacitance

In the case of Stratix® II, individual logic array structures within different architectural features conduct very small currents (picoamps or less) for very short durations (< 50 ps). Although these currents are small, when added up across the entire device they can add up to several amperes of current. Considering that these minute current transitions can occur hundreds of millions of times per second, along with the existence of millions of individual switches carrying out these transitions, bypass capacitor calculation is based on an average energy storage requirement. High-frequency capacitor values can be approximated with:

logic array power = equivalent switched logic array capacitance × V_CCINT² × clock frequency

or

equivalent switched logic array capacitance = (logic array power) / (V_CCINT² × clock frequency)

The equivalent switched logic array capacitance is the equivalent switched capacitance of the entire Stratix II logic array powered by V_CCINT. In order to reduce power noise, the V_CCINT power supply bypass capacitor must be significantly larger than the equivalent switched logic array capacitance. High-frequency bypass capacitors should be 25 to 100 times larger than the equivalent switched logic array capacitance. A factor of 50 will result in a 2 percent variation of V_CCINT.

High-frequency bypass capacitance = <25 to 100> × equivalent switched logic array capacitance

Every V_CCINT and ground pin pair should have a high-frequency bypass capacitor. To determine the optimum size of each high-frequency bypass capacitor, divide the total high-frequency bypass capacitance by the number of V_CCINT pins on the device, and round up to the next commonly available value. Therefore, the minimum size of each high-frequency V_CCINT capacitor is:

Consider the following example:

• Device V_CCINT power = 5 W
  
• V_CCINT = 1.2 V
• System clock frequency = 150 MHz
• High-frequency bypass capacitor multiplier = 50
• Number of device V_CCINT pins = 36

The capacitor size should be at least 0.032 µF. Given this example, the designer should select individual high-frequency capacitors at least this large.

The medium-frequency capacitors should be tantalum capacitors from 47 µF to 100 µF. If tantalum is not available, low-inductance aluminum electrolytic capacitors can be used. Stratix II devices require at least four medium-frequency capacitors mounted within 3 cm of the device. In addition, at least one low-frequency capacitor (470 µF to 3300 µF) is required on the PCB.

V_CCIO Bypass Capacitance

Similar to V_CCINT considerations, V_CCIO bypass requirements are also based on an average energy storage requirement. The loads driven by the FPGA or CPLD device determine the size of the equivalent switched capacitance. Since different I/O banks can operate at different voltages and different switching frequencies, designers should consider bypassing networks individually, using the equations below to determine high-frequency capacitor requirements.

In order to reduce the amount of V_CCIO noise, bypass capacitance must be significantly greater than the total output load capacitance. High-frequency bypass capacitance should be 25 to 100 times the total load capacitance. Every V_CCIO and ground pair should have a high-frequency bypass capacitor to provide immediate current needs when the device has a large current draw. The following equations determine the optimum size of each capacitor:

Consider the following example:

• Number of loads = 40 signals
• Average load value = 10pF
• High-frequency bypass capacitor multiplier = 50
• Number of device V_CCIO pins = 5

The capacitor size should be 0.004 µF. Given this example, the designer should select individual high-frequency capacitors at least this large. The next larger available capacitor size should be chosen (0.047 µF or 0.01 µF).

Medium-frequency capacitors should be tantalum capacitors from 47 µF to 100 µF. One middle-frequency capacitor is required for every two V_CCIO banks. If tantalum capacitors are not available, low-inductance aluminum electrolytic capacitors can be used. These capacitors should be located within 3 cm of the V_CCIO pin connections. Lastly, at least one low-frequency capacitor (470 µF to 3,300 µF) is required on the PCB for each V_CCIO voltage level.