Timing Analyzer Set Multicycle Path Command

By default, the Timing Analyzer uses a single-cycle analysis. When analyzing a path, the setup launch and latch edge times are determined by finding the closest two active edges in the respective waveforms. For a hold analysis, the timing analyzer analyzes the path against two timing conditions for every possible setup relationship (not just the worst-case). Therefore, the hold launch and latch times may be completely unrelated to the setup launch and latch edges.

A multicycle constraint relaxes setup or hold relationships by the specified number of clock cycles based on the source (-start) or destination (-end) clock. An end multicycle constraint of 2 extends the worst-case setup latch edge by one destination clock period.

Hold multicycle constraints are based on the default hold position (the default value is 0). An end hold multicycle constraint of 1 effectively subtracts one destination clock period from the default hold latch edge. You can use the set_multicycle_path command to specify the multicycle constraints in the design. The following list shows the set_multicycle_path command including the available options:

set_multicycle_path
     [-setup | -hold]
     [-start | -end]
     [-from <from list>]
     [-to <to list>]
     [-thru <thru list>]
     <path multiplier>

Table 1 describes the options for the set_multicycle_path command.

When the objects are timing nodes, the multicycle constraint only applies to the path between the two nodes. When an object is a clock, the multicycle constraint applies to all paths where the source node (for - from) or destination node (for -to) is clocked by the clock.