In a source-synchronous output interface, the FPGA sources the clock for the destination device. In a source-synchronous interface that is edge-aligned, the clock transition occurs at the same time as the data transition. Figure 1 shows a sample source-synchronous output interface.
Use the following steps to constrain an edge-aligned source-synchronous output interface:
- Create base and generated clocks
- Add output delay constraints
- Add false path exceptions to exclude invalid paths from timing analysis and reporting
For more details about any of these steps, or the calculations and constraints described below, refer to Constraining and Analyzing Source-Synchronous Interfaces(PDF).
Clocks
A base clock is required on the input port of the FPGA.
Generated clocks are required on all phase-locked loop (PLL) outputs. A double data rate edge-aligned source-synchronous output aligns the output clock with the data clock.
A generated clock is required on the output clock port of the FPGA. The generated clock is the clock reference for output delay values for the data bus.
Output Delay Constraints
You can use a maximum skew specification to calculate output delay values. The maximum skew specification indicates the allowable time variation for individual bits of a data bus to leave the FPGA.
The value of the output maximum delay is clock period - maximum skew value.
The value of the output minimum delay is maximum skew value.
False Path Exceptions
In this edge-aligned example, data is transferred on rise-rise and fall-fall source and destination clock transitions. Use false path exceptions to cut rise-fall and fall-rise clock transitions, because data is not transferred on opposite-edge clock transitions.
Sample SDC File
# Create a base clock on the input port of the FPGA, with a 10 ns period
create_clock -name input_clock -period 10 [get_ports clk_in]
# Create generated clocks on the PLL outputs
# Output clk[0] drives the data register
# Output clk[1] drives the output clock port
create_generated_clock -name data_clock -source [get_pins pll|inclk[0]] \
[get_pins pll|clk[0]]
create_generated_clock -name clock_clock -source [get_pins pll|inclk[0] \
[get_pins pll|clk[1]]
# Create the generated clock on the output clock port of the FPGA
create_generated_clock -name output_clock -source [get_pins pll|clk[1]] \
[get_ports clk_out]
# Add maximum and minimum output delay constraints
# assuming a skew requirement of +/- 250ps
# Use the equations for the output delay values listed above
set_output_delay -max -clock output_clock [expr { 10 - 0.250 }] \
[get_ports data_out*]
set_output_delay -max -clock output_clock -clock_fall \
[expr { 10 - 0.250 }] [get_ports data_out*] -add
set_output_delay -min -clock output_clock 0.250 [get_ports data_out*]
set_output_delay -min -clock output_clock -clock_fall 0.250 \
[get_ports data_out*] -add
# Add false path exceptions for cross-clock transfers
set_false_path -setup -end -rise_from [get_clocks data_clock] \
-fall_to [get_clocks output_clock]
set_false_path -setup -end -fall_from [get_clocks data_clock] \
-rise_to [get_clocks output_clock]
set_false_path -hold -end -rise_from [get_clocks data_clock] \
-fall_to [get_clocks output_clock]
set_false_path -hold -end -fall_from [get_clocks data_clock] \
-rise_to [get_clocks output_clock]