A source-synchronous input interface is constrained in a similar way as a system-synchronous input interface. The FPGA receives a clock and uses that clock to latch the input data. In a source-synchronous interface that is center-aligned, the clock transition occurs in the middle of the data valid window. Figure 1 shows a sample source-synchronous input interface.
Use the following steps to constrain a center-aligned source-synchronous input interface:
- Create virtual, base, and generated clocks
- Add input delay constraints
- Add false path exceptions to exclude invalid paths from timing analysis and reporting
For more details about any of these steps, or the calculations and constraints described below, refer to AN 433: Constraining and Analyzing Source-Synchronous Interfaces (PDF).
Clocks
A virtual clock models the clock in the external device that drives the data registers to transmit data to the FPGA.
A base clock is required on the input port of the FPGA. The base clock describes the clock characteristics at the clock input of the FPGA. If the input clock is center aligned with the data, you must use the -waveform option to specify the rising and falling clock edges that correspond to the clock phase shift.
Generated clocks are required on all phase-locked loop (PLL) outputs.
Input Delay Constraints
You can use a maximum skew specification to calculate input delay values. The maximum skew specification indicates the allowable time variation for individual bits of a data bus to arrive at the FPGA.
The value of the input maximum delay is maximum skew value.
The value of the input minimum delay is -maximum skew value.
False Path Exceptions
In this center-aligned example, data is transferred on rise-rise and fall-fall source and destination clock transitions. Use false path exceptions to cut rise-fall and fall-rise clock transitions, because data is not transferred on opposite-edge clock transitions.
Sample SDC File
# Create a virtual clock to describe the data clock in
# the external device.
create_clock -name virt_clk -period 10
# Create a base clock on the input port of the FPGA, with a 10 ns period
# and a 90 degree phase shift because the interface is center aligned
create_clock -name input_clock -period 10 -waveform { 2.5 7.5 } [get_ports clk_in]
# Create generated clocks on the PLL outputs
create_generated_clock -name data_clock -source [get_pins pll|inclk[0]] \
[get_pins pll|clk[0]]
# Add maximum and minimum input delay constraints
# assuming a skew requirement of +/- 250ps
# Use the equations for the input delay values listed above
set_input_delay -max -clock virt_clk 0.250 [get_ports data_in*]
set_input_delay -min -clock virt_clk -0.250 [get_ports data_in*]
set_input_delay -max -clock virt_clk -clock_fall \
0.250 [get_ports data_in*] -add
set_input_delay -min -clock virt_clk -clock_fall \
-0.250 [get_ports data_in*] -add
# Add false path exceptions for cross-clock transfers
set_false_path -setup -end -rise_from [get_clocks virt_clk] \
-fall_to [get_clocks data_clock]
set_false_path -setup -end -fall_from [get_clocks virt_clk] \
-rise_to [get_clocks data_clock]
set_false_path -hold -end -rise_from [get_clocks virt_clk] \
-rise_to [get_clocks data_clock]
set_false_path -hold -end -fall_from [get_clocks virt_clk] \
-fall_to [get_clocks data_clock]