VHDL: Unsigned Multiply-Adder

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This example describes an 8-bit unsigned multiply-adder design with registered I/O ports in VHDL. Synthesis tools detect multiply-adder designs in HDL code and infer altmult_add megafunction.

Figure 1. Unsigned multiply-adder top-level diagram.

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Table 1. Unsigned Multiply-Adder Port Listing

Port Name Type Description
a, b, c, d Input 8-bit inputs to multiply-adder unit
clk Input Clock
aclr Input Asynchronous clear
result Output 16-bit output of multiply-adder unit
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