This example describes a parameterized single clock synchronous 16-bit x 8-bit RAM with separate read and write addresses in VHDL. Synthesis tools detect single port RAM designs in HDL code and infer altsyncram or altdpram megafunctions depending on target device architecture.
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Table 1. Single Clock Synchronous RAM Port Listing
| Port Name | Type | Description |
|---|---|---|
| data | Input | 8-bit data input to RAM |
| clock | Input | Clock |
| read_address | Input | 4-bit read address input |
| write_address | Input | 4-bit write address input |
| we | Input | Write enable input |
| q | Output | 8-bit data output of RAM |