VHDL: Gray Counter

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This example describes an 8-bit Gray-code counter design in VHDL. The Gray code outputs differ in only one bit for every two successive values.

Figure 1. Gray counter top-level diagram.

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Table 1. Gray Counter Port Listing

Port Name Type Description
clk Input Clock input
reset Input Reset input
enable Input Enable input
gray_count[7:0] Output 8-bit data output
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